Lines Matching defs:MO
45 const MCOperand &MO = MI.getOperand(OpNo);
47 if (MO.isReg() || MO.isImm())
48 return getMachineOpValue(MI, MO, Fixups, STI);
51 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
155 const MCOperand &MO = MI.getOperand(OpNo);
156 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
159 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
168 const MCOperand &MO = MI.getOperand(OpNo);
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
172 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
181 const MCOperand &MO = MI.getOperand(OpNo);
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
185 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
203 const MCOperand &MO = MI.getOperand(OpNo);
204 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
207 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
216 const MCOperand &MO = MI.getOperand(OpNo);
217 assert(!MO.isReg() && "Not expecting a register for this operand.");
218 if (MO.isImm())
219 return getMachineOpValue(MI, MO, Fixups, STI);
222 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
245 const MCOperand &MO = MI.getOperand(OpNo);
246 if (MO.isImm())
247 return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
250 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
259 const MCOperand &MO = MI.getOperand(OpNo);
260 if (MO.isImm())
261 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
264 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
273 const MCOperand &MO = MI.getOperand(OpNo);
274 if (MO.isImm()) {
275 assert(!(MO.getImm() % 16) &&
277 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
281 Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
292 const MCOperand &MO = MI.getOperand(OpNo);
294 assert(MO.isImm() && "Expecting an immediate operand.");
295 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
297 unsigned DX = (MO.getImm() >> 3) & 0x3F;
315 const MCOperand &MO = MI.getOperand(OpNo);
316 if (!MO.isExpr())
317 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
319 // At this point in the function it is known that MO is of type MCExpr.
322 const MCExpr *Expr = MO.getExpr();
389 const MCOperand &MO = MI.getOperand(OpNo);
390 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
398 const MCOperand &MO = MI.getOperand(OpNo);
399 assert(MO.isImm());
400 return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
408 const MCOperand &MO = MI.getOperand(OpNo);
409 assert(MO.isImm());
410 return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
418 const MCOperand &MO = MI.getOperand(OpNo);
419 assert(MO.isImm());
420 return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
426 const MCOperand &MO = MI.getOperand(OpNo);
427 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
433 const MCExpr *Expr = MO.getExpr();
449 const MCOperand &MO = MI.getOperand(OpNo+1);
450 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
459 const MCOperand &MO = MI.getOperand(OpNo);
462 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
463 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
470 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
473 if (&Op == &MO)
481 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
484 if (MO.isReg()) {
489 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
490 unsigned OpNo = getOpIdxForMO(MI, MO);
492 PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo);
496 assert(MO.isImm() &&
498 return MO.getImm();