Lines Matching defs:MI
42 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
45 const MCOperand &MO = MI.getOperand(OpNo);
48 return getMachineOpValue(MI, MO, Fixups, STI);
52 (isNoTOCCallInstr(MI)
60 bool PPCMCCodeEmitter::isNoTOCCallInstr(const MCInst &MI) const {
61 unsigned Opcode = MI.getOpcode();
152 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
155 const MCOperand &MO = MI.getOperand(OpNo);
156 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
165 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
168 const MCOperand &MO = MI.getOperand(OpNo);
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
178 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
181 const MCOperand &MO = MI.getOperand(OpNo);
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
191 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
194 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
195 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
200 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
203 const MCOperand &MO = MI.getOperand(OpNo);
204 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
212 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
216 const MCOperand &MO = MI.getOperand(OpNo);
219 return getMachineOpValue(MI, MO, Fixups, STI);
227 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
230 return getImm34Encoding(MI, OpNo, Fixups, STI,
235 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
238 return getImm34Encoding(MI, OpNo, Fixups, STI,
242 unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
245 const MCOperand &MO = MI.getOperand(OpNo);
247 return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
256 PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
259 const MCOperand &MO = MI.getOperand(OpNo);
261 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
270 PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
273 const MCOperand &MO = MI.getOperand(OpNo);
277 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
287 PPCMCCodeEmitter::getDispRIHashEncoding(const MCInst &MI, unsigned OpNo,
292 const MCOperand &MO = MI.getOperand(OpNo);
302 PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
315 const MCOperand &MO = MI.getOperand(OpNo);
317 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
385 PPCMCCodeEmitter::getDispRI34Encoding(const MCInst &MI, unsigned OpNo,
389 const MCOperand &MO = MI.getOperand(OpNo);
390 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
394 PPCMCCodeEmitter::getDispSPE8Encoding(const MCInst &MI, unsigned OpNo,
398 const MCOperand &MO = MI.getOperand(OpNo);
400 return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
404 PPCMCCodeEmitter::getDispSPE4Encoding(const MCInst &MI, unsigned OpNo,
408 const MCOperand &MO = MI.getOperand(OpNo);
410 return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
414 PPCMCCodeEmitter::getDispSPE2Encoding(const MCInst &MI, unsigned OpNo,
418 const MCOperand &MO = MI.getOperand(OpNo);
420 return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
423 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
426 const MCOperand &MO = MI.getOperand(OpNo);
427 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
443 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
449 const MCOperand &MO = MI.getOperand(OpNo+1);
452 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
456 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
459 const MCOperand &MO = MI.getOperand(OpNo);
460 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
461 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
470 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
471 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
472 const MCOperand &Op = MI.getOperand(i);
481 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
487 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
488 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
490 unsigned OpNo = getOpIdxForMO(MI, MO);
492 PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo);
501 void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI,
505 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
508 unsigned Size = getInstSizeInBytes(MI);
531 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
532 unsigned Opcode = MI.getOpcode();
537 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
538 return MCII.get(MI.getOpcode()).TSFlags & PPCII::Prefixed;