Lines Matching full:case
77 case NVPTX::SULD_1D_I8_CLAMP_R:
79 case NVPTX::SULD_1D_I16_CLAMP_R:
81 case NVPTX::SULD_1D_I32_CLAMP_R:
83 case NVPTX::SULD_1D_I64_CLAMP_R:
85 case NVPTX::SULD_1D_ARRAY_I8_CLAMP_R:
87 case NVPTX::SULD_1D_ARRAY_I16_CLAMP_R:
89 case NVPTX::SULD_1D_ARRAY_I32_CLAMP_R:
91 case NVPTX::SULD_1D_ARRAY_I64_CLAMP_R:
93 case NVPTX::SULD_2D_I8_CLAMP_R:
95 case NVPTX::SULD_2D_I16_CLAMP_R:
97 case NVPTX::SULD_2D_I32_CLAMP_R:
99 case NVPTX::SULD_2D_I64_CLAMP_R:
101 case NVPTX::SULD_2D_ARRAY_I8_CLAMP_R:
103 case NVPTX::SULD_2D_ARRAY_I16_CLAMP_R:
105 case NVPTX::SULD_2D_ARRAY_I32_CLAMP_R:
107 case NVPTX::SULD_2D_ARRAY_I64_CLAMP_R:
109 case NVPTX::SULD_3D_I8_CLAMP_R:
111 case NVPTX::SULD_3D_I16_CLAMP_R:
113 case NVPTX::SULD_3D_I32_CLAMP_R:
115 case NVPTX::SULD_3D_I64_CLAMP_R:
117 case NVPTX::SULD_1D_V2I8_CLAMP_R:
119 case NVPTX::SULD_1D_V2I16_CLAMP_R:
121 case NVPTX::SULD_1D_V2I32_CLAMP_R:
123 case NVPTX::SULD_1D_V2I64_CLAMP_R:
125 case NVPTX::SULD_1D_ARRAY_V2I8_CLAMP_R:
127 case NVPTX::SULD_1D_ARRAY_V2I16_CLAMP_R:
129 case NVPTX::SULD_1D_ARRAY_V2I32_CLAMP_R:
131 case NVPTX::SULD_1D_ARRAY_V2I64_CLAMP_R:
133 case NVPTX::SULD_2D_V2I8_CLAMP_R:
135 case NVPTX::SULD_2D_V2I16_CLAMP_R:
137 case NVPTX::SULD_2D_V2I32_CLAMP_R:
139 case NVPTX::SULD_2D_V2I64_CLAMP_R:
141 case NVPTX::SULD_2D_ARRAY_V2I8_CLAMP_R:
143 case NVPTX::SULD_2D_ARRAY_V2I16_CLAMP_R:
145 case NVPTX::SULD_2D_ARRAY_V2I32_CLAMP_R:
147 case NVPTX::SULD_2D_ARRAY_V2I64_CLAMP_R:
149 case NVPTX::SULD_3D_V2I8_CLAMP_R:
151 case NVPTX::SULD_3D_V2I16_CLAMP_R:
153 case NVPTX::SULD_3D_V2I32_CLAMP_R:
155 case NVPTX::SULD_3D_V2I64_CLAMP_R:
157 case NVPTX::SULD_1D_V4I8_CLAMP_R:
159 case NVPTX::SULD_1D_V4I16_CLAMP_R:
161 case NVPTX::SULD_1D_V4I32_CLAMP_R:
163 case NVPTX::SULD_1D_ARRAY_V4I8_CLAMP_R:
165 case NVPTX::SULD_1D_ARRAY_V4I16_CLAMP_R:
167 case NVPTX::SULD_1D_ARRAY_V4I32_CLAMP_R:
169 case NVPTX::SULD_2D_V4I8_CLAMP_R:
171 case NVPTX::SULD_2D_V4I16_CLAMP_R:
173 case NVPTX::SULD_2D_V4I32_CLAMP_R:
175 case NVPTX::SULD_2D_ARRAY_V4I8_CLAMP_R:
177 case NVPTX::SULD_2D_ARRAY_V4I16_CLAMP_R:
179 case NVPTX::SULD_2D_ARRAY_V4I32_CLAMP_R:
181 case NVPTX::SULD_3D_V4I8_CLAMP_R:
183 case NVPTX::SULD_3D_V4I16_CLAMP_R:
185 case NVPTX::SULD_3D_V4I32_CLAMP_R:
187 case NVPTX::SULD_1D_I8_TRAP_R:
189 case NVPTX::SULD_1D_I16_TRAP_R:
191 case NVPTX::SULD_1D_I32_TRAP_R:
193 case NVPTX::SULD_1D_I64_TRAP_R:
195 case NVPTX::SULD_1D_ARRAY_I8_TRAP_R:
197 case NVPTX::SULD_1D_ARRAY_I16_TRAP_R:
199 case NVPTX::SULD_1D_ARRAY_I32_TRAP_R:
201 case NVPTX::SULD_1D_ARRAY_I64_TRAP_R:
203 case NVPTX::SULD_2D_I8_TRAP_R:
205 case NVPTX::SULD_2D_I16_TRAP_R:
207 case NVPTX::SULD_2D_I32_TRAP_R:
209 case NVPTX::SULD_2D_I64_TRAP_R:
211 case NVPTX::SULD_2D_ARRAY_I8_TRAP_R:
213 case NVPTX::SULD_2D_ARRAY_I16_TRAP_R:
215 case NVPTX::SULD_2D_ARRAY_I32_TRAP_R:
217 case NVPTX::SULD_2D_ARRAY_I64_TRAP_R:
219 case NVPTX::SULD_3D_I8_TRAP_R:
221 case NVPTX::SULD_3D_I16_TRAP_R:
223 case NVPTX::SULD_3D_I32_TRAP_R:
225 case NVPTX::SULD_3D_I64_TRAP_R:
227 case NVPTX::SULD_1D_V2I8_TRAP_R:
229 case NVPTX::SULD_1D_V2I16_TRAP_R:
231 case NVPTX::SULD_1D_V2I32_TRAP_R:
233 case NVPTX::SULD_1D_V2I64_TRAP_R:
235 case NVPTX::SULD_1D_ARRAY_V2I8_TRAP_R:
237 case NVPTX::SULD_1D_ARRAY_V2I16_TRAP_R:
239 case NVPTX::SULD_1D_ARRAY_V2I32_TRAP_R:
241 case NVPTX::SULD_1D_ARRAY_V2I64_TRAP_R:
243 case NVPTX::SULD_2D_V2I8_TRAP_R:
245 case NVPTX::SULD_2D_V2I16_TRAP_R:
247 case NVPTX::SULD_2D_V2I32_TRAP_R:
249 case NVPTX::SULD_2D_V2I64_TRAP_R:
251 case NVPTX::SULD_2D_ARRAY_V2I8_TRAP_R:
253 case NVPTX::SULD_2D_ARRAY_V2I16_TRAP_R:
255 case NVPTX::SULD_2D_ARRAY_V2I32_TRAP_R:
257 case NVPTX::SULD_2D_ARRAY_V2I64_TRAP_R:
259 case NVPTX::SULD_3D_V2I8_TRAP_R:
261 case NVPTX::SULD_3D_V2I16_TRAP_R:
263 case NVPTX::SULD_3D_V2I32_TRAP_R:
265 case NVPTX::SULD_3D_V2I64_TRAP_R:
267 case NVPTX::SULD_1D_V4I8_TRAP_R:
269 case NVPTX::SULD_1D_V4I16_TRAP_R:
271 case NVPTX::SULD_1D_V4I32_TRAP_R:
273 case NVPTX::SULD_1D_ARRAY_V4I8_TRAP_R:
275 case NVPTX::SULD_1D_ARRAY_V4I16_TRAP_R:
277 case NVPTX::SULD_1D_ARRAY_V4I32_TRAP_R:
279 case NVPTX::SULD_2D_V4I8_TRAP_R:
281 case NVPTX::SULD_2D_V4I16_TRAP_R:
283 case NVPTX::SULD_2D_V4I32_TRAP_R:
285 case NVPTX::SULD_2D_ARRAY_V4I8_TRAP_R:
287 case NVPTX::SULD_2D_ARRAY_V4I16_TRAP_R:
289 case NVPTX::SULD_2D_ARRAY_V4I32_TRAP_R:
291 case NVPTX::SULD_3D_V4I8_TRAP_R:
293 case NVPTX::SULD_3D_V4I16_TRAP_R:
295 case NVPTX::SULD_3D_V4I32_TRAP_R:
297 case NVPTX::SULD_1D_I8_ZERO_R:
299 case NVPTX::SULD_1D_I16_ZERO_R:
301 case NVPTX::SULD_1D_I32_ZERO_R:
303 case NVPTX::SULD_1D_I64_ZERO_R:
305 case NVPTX::SULD_1D_ARRAY_I8_ZERO_R:
307 case NVPTX::SULD_1D_ARRAY_I16_ZERO_R:
309 case NVPTX::SULD_1D_ARRAY_I32_ZERO_R:
311 case NVPTX::SULD_1D_ARRAY_I64_ZERO_R:
313 case NVPTX::SULD_2D_I8_ZERO_R:
315 case NVPTX::SULD_2D_I16_ZERO_R:
317 case NVPTX::SULD_2D_I32_ZERO_R:
319 case NVPTX::SULD_2D_I64_ZERO_R:
321 case NVPTX::SULD_2D_ARRAY_I8_ZERO_R:
323 case NVPTX::SULD_2D_ARRAY_I16_ZERO_R:
325 case NVPTX::SULD_2D_ARRAY_I32_ZERO_R:
327 case NVPTX::SULD_2D_ARRAY_I64_ZERO_R:
329 case NVPTX::SULD_3D_I8_ZERO_R:
331 case NVPTX::SULD_3D_I16_ZERO_R:
333 case NVPTX::SULD_3D_I32_ZERO_R:
335 case NVPTX::SULD_3D_I64_ZERO_R:
337 case NVPTX::SULD_1D_V2I8_ZERO_R:
339 case NVPTX::SULD_1D_V2I16_ZERO_R:
341 case NVPTX::SULD_1D_V2I32_ZERO_R:
343 case NVPTX::SULD_1D_V2I64_ZERO_R:
345 case NVPTX::SULD_1D_ARRAY_V2I8_ZERO_R:
347 case NVPTX::SULD_1D_ARRAY_V2I16_ZERO_R:
349 case NVPTX::SULD_1D_ARRAY_V2I32_ZERO_R:
351 case NVPTX::SULD_1D_ARRAY_V2I64_ZERO_R:
353 case NVPTX::SULD_2D_V2I8_ZERO_R:
355 case NVPTX::SULD_2D_V2I16_ZERO_R:
357 case NVPTX::SULD_2D_V2I32_ZERO_R:
359 case NVPTX::SULD_2D_V2I64_ZERO_R:
361 case NVPTX::SULD_2D_ARRAY_V2I8_ZERO_R:
363 case NVPTX::SULD_2D_ARRAY_V2I16_ZERO_R:
365 case NVPTX::SULD_2D_ARRAY_V2I32_ZERO_R:
367 case NVPTX::SULD_2D_ARRAY_V2I64_ZERO_R:
369 case NVPTX::SULD_3D_V2I8_ZERO_R:
371 case NVPTX::SULD_3D_V2I16_ZERO_R:
373 case NVPTX::SULD_3D_V2I32_ZERO_R:
375 case NVPTX::SULD_3D_V2I64_ZERO_R:
377 case NVPTX::SULD_1D_V4I8_ZERO_R:
379 case NVPTX::SULD_1D_V4I16_ZERO_R:
381 case NVPTX::SULD_1D_V4I32_ZERO_R:
383 case NVPTX::SULD_1D_ARRAY_V4I8_ZERO_R:
385 case NVPTX::SULD_1D_ARRAY_V4I16_ZERO_R:
387 case NVPTX::SULD_1D_ARRAY_V4I32_ZERO_R:
389 case NVPTX::SULD_2D_V4I8_ZERO_R:
391 case NVPTX::SULD_2D_V4I16_ZERO_R:
393 case NVPTX::SULD_2D_V4I32_ZERO_R:
395 case NVPTX::SULD_2D_ARRAY_V4I8_ZERO_R:
397 case NVPTX::SULD_2D_ARRAY_V4I16_ZERO_R:
399 case NVPTX::SULD_2D_ARRAY_V4I32_ZERO_R:
401 case NVPTX::SULD_3D_V4I8_ZERO_R:
403 case NVPTX::SULD_3D_V4I16_ZERO_R:
405 case NVPTX::SULD_3D_V4I32_ZERO_R:
414 case NVPTX::SUST_B_1D_B8_CLAMP_R:
416 case NVPTX::SUST_B_1D_B16_CLAMP_R:
418 case NVPTX::SUST_B_1D_B32_CLAMP_R:
420 case NVPTX::SUST_B_1D_B64_CLAMP_R:
422 case NVPTX::SUST_B_1D_V2B8_CLAMP_R:
424 case NVPTX::SUST_B_1D_V2B16_CLAMP_R:
426 case NVPTX::SUST_B_1D_V2B32_CLAMP_R:
428 case NVPTX::SUST_B_1D_V2B64_CLAMP_R:
430 case NVPTX::SUST_B_1D_V4B8_CLAMP_R:
432 case NVPTX::SUST_B_1D_V4B16_CLAMP_R:
434 case NVPTX::SUST_B_1D_V4B32_CLAMP_R:
436 case NVPTX::SUST_B_1D_ARRAY_B8_CLAMP_R:
438 case NVPTX::SUST_B_1D_ARRAY_B16_CLAMP_R:
440 case NVPTX::SUST_B_1D_ARRAY_B32_CLAMP_R:
442 case NVPTX::SUST_B_1D_ARRAY_B64_CLAMP_R:
444 case NVPTX::SUST_B_1D_ARRAY_V2B8_CLAMP_R:
446 case NVPTX::SUST_B_1D_ARRAY_V2B16_CLAMP_R:
448 case NVPTX::SUST_B_1D_ARRAY_V2B32_CLAMP_R:
450 case NVPTX::SUST_B_1D_ARRAY_V2B64_CLAMP_R:
452 case NVPTX::SUST_B_1D_ARRAY_V4B8_CLAMP_R:
454 case NVPTX::SUST_B_1D_ARRAY_V4B16_CLAMP_R:
456 case NVPTX::SUST_B_1D_ARRAY_V4B32_CLAMP_R:
458 case NVPTX::SUST_B_2D_B8_CLAMP_R:
460 case NVPTX::SUST_B_2D_B16_CLAMP_R:
462 case NVPTX::SUST_B_2D_B32_CLAMP_R:
464 case NVPTX::SUST_B_2D_B64_CLAMP_R:
466 case NVPTX::SUST_B_2D_V2B8_CLAMP_R:
468 case NVPTX::SUST_B_2D_V2B16_CLAMP_R:
470 case NVPTX::SUST_B_2D_V2B32_CLAMP_R:
472 case NVPTX::SUST_B_2D_V2B64_CLAMP_R:
474 case NVPTX::SUST_B_2D_V4B8_CLAMP_R:
476 case NVPTX::SUST_B_2D_V4B16_CLAMP_R:
478 case NVPTX::SUST_B_2D_V4B32_CLAMP_R:
480 case NVPTX::SUST_B_2D_ARRAY_B8_CLAMP_R:
482 case NVPTX::SUST_B_2D_ARRAY_B16_CLAMP_R:
484 case NVPTX::SUST_B_2D_ARRAY_B32_CLAMP_R:
486 case NVPTX::SUST_B_2D_ARRAY_B64_CLAMP_R:
488 case NVPTX::SUST_B_2D_ARRAY_V2B8_CLAMP_R:
490 case NVPTX::SUST_B_2D_ARRAY_V2B16_CLAMP_R:
492 case NVPTX::SUST_B_2D_ARRAY_V2B32_CLAMP_R:
494 case NVPTX::SUST_B_2D_ARRAY_V2B64_CLAMP_R:
496 case NVPTX::SUST_B_2D_ARRAY_V4B8_CLAMP_R:
498 case NVPTX::SUST_B_2D_ARRAY_V4B16_CLAMP_R:
500 case NVPTX::SUST_B_2D_ARRAY_V4B32_CLAMP_R:
502 case NVPTX::SUST_B_3D_B8_CLAMP_R:
504 case NVPTX::SUST_B_3D_B16_CLAMP_R:
506 case NVPTX::SUST_B_3D_B32_CLAMP_R:
508 case NVPTX::SUST_B_3D_B64_CLAMP_R:
510 case NVPTX::SUST_B_3D_V2B8_CLAMP_R:
512 case NVPTX::SUST_B_3D_V2B16_CLAMP_R:
514 case NVPTX::SUST_B_3D_V2B32_CLAMP_R:
516 case NVPTX::SUST_B_3D_V2B64_CLAMP_R:
518 case NVPTX::SUST_B_3D_V4B8_CLAMP_R:
520 case NVPTX::SUST_B_3D_V4B16_CLAMP_R:
522 case NVPTX::SUST_B_3D_V4B32_CLAMP_R:
524 case NVPTX::SUST_B_1D_B8_TRAP_R:
526 case NVPTX::SUST_B_1D_B16_TRAP_R:
528 case NVPTX::SUST_B_1D_B32_TRAP_R:
530 case NVPTX::SUST_B_1D_B64_TRAP_R:
532 case NVPTX::SUST_B_1D_V2B8_TRAP_R:
534 case NVPTX::SUST_B_1D_V2B16_TRAP_R:
536 case NVPTX::SUST_B_1D_V2B32_TRAP_R:
538 case NVPTX::SUST_B_1D_V2B64_TRAP_R:
540 case NVPTX::SUST_B_1D_V4B8_TRAP_R:
542 case NVPTX::SUST_B_1D_V4B16_TRAP_R:
544 case NVPTX::SUST_B_1D_V4B32_TRAP_R:
546 case NVPTX::SUST_B_1D_ARRAY_B8_TRAP_R:
548 case NVPTX::SUST_B_1D_ARRAY_B16_TRAP_R:
550 case NVPTX::SUST_B_1D_ARRAY_B32_TRAP_R:
552 case NVPTX::SUST_B_1D_ARRAY_B64_TRAP_R:
554 case NVPTX::SUST_B_1D_ARRAY_V2B8_TRAP_R:
556 case NVPTX::SUST_B_1D_ARRAY_V2B16_TRAP_R:
558 case NVPTX::SUST_B_1D_ARRAY_V2B32_TRAP_R:
560 case NVPTX::SUST_B_1D_ARRAY_V2B64_TRAP_R:
562 case NVPTX::SUST_B_1D_ARRAY_V4B8_TRAP_R:
564 case NVPTX::SUST_B_1D_ARRAY_V4B16_TRAP_R:
566 case NVPTX::SUST_B_1D_ARRAY_V4B32_TRAP_R:
568 case NVPTX::SUST_B_2D_B8_TRAP_R:
570 case NVPTX::SUST_B_2D_B16_TRAP_R:
572 case NVPTX::SUST_B_2D_B32_TRAP_R:
574 case NVPTX::SUST_B_2D_B64_TRAP_R:
576 case NVPTX::SUST_B_2D_V2B8_TRAP_R:
578 case NVPTX::SUST_B_2D_V2B16_TRAP_R:
580 case NVPTX::SUST_B_2D_V2B32_TRAP_R:
582 case NVPTX::SUST_B_2D_V2B64_TRAP_R:
584 case NVPTX::SUST_B_2D_V4B8_TRAP_R:
586 case NVPTX::SUST_B_2D_V4B16_TRAP_R:
588 case NVPTX::SUST_B_2D_V4B32_TRAP_R:
590 case NVPTX::SUST_B_2D_ARRAY_B8_TRAP_R:
592 case NVPTX::SUST_B_2D_ARRAY_B16_TRAP_R:
594 case NVPTX::SUST_B_2D_ARRAY_B32_TRAP_R:
596 case NVPTX::SUST_B_2D_ARRAY_B64_TRAP_R:
598 case NVPTX::SUST_B_2D_ARRAY_V2B8_TRAP_R:
600 case NVPTX::SUST_B_2D_ARRAY_V2B16_TRAP_R:
602 case NVPTX::SUST_B_2D_ARRAY_V2B32_TRAP_R:
604 case NVPTX::SUST_B_2D_ARRAY_V2B64_TRAP_R:
606 case NVPTX::SUST_B_2D_ARRAY_V4B8_TRAP_R:
608 case NVPTX::SUST_B_2D_ARRAY_V4B16_TRAP_R:
610 case NVPTX::SUST_B_2D_ARRAY_V4B32_TRAP_R:
612 case NVPTX::SUST_B_3D_B8_TRAP_R:
614 case NVPTX::SUST_B_3D_B16_TRAP_R:
616 case NVPTX::SUST_B_3D_B32_TRAP_R:
618 case NVPTX::SUST_B_3D_B64_TRAP_R:
620 case NVPTX::SUST_B_3D_V2B8_TRAP_R:
622 case NVPTX::SUST_B_3D_V2B16_TRAP_R:
624 case NVPTX::SUST_B_3D_V2B32_TRAP_R:
626 case NVPTX::SUST_B_3D_V2B64_TRAP_R:
628 case NVPTX::SUST_B_3D_V4B8_TRAP_R:
630 case NVPTX::SUST_B_3D_V4B16_TRAP_R:
632 case NVPTX::SUST_B_3D_V4B32_TRAP_R:
634 case NVPTX::SUST_B_1D_B8_ZERO_R:
636 case NVPTX::SUST_B_1D_B16_ZERO_R:
638 case NVPTX::SUST_B_1D_B32_ZERO_R:
640 case NVPTX::SUST_B_1D_B64_ZERO_R:
642 case NVPTX::SUST_B_1D_V2B8_ZERO_R:
644 case NVPTX::SUST_B_1D_V2B16_ZERO_R:
646 case NVPTX::SUST_B_1D_V2B32_ZERO_R:
648 case NVPTX::SUST_B_1D_V2B64_ZERO_R:
650 case NVPTX::SUST_B_1D_V4B8_ZERO_R:
652 case NVPTX::SUST_B_1D_V4B16_ZERO_R:
654 case NVPTX::SUST_B_1D_V4B32_ZERO_R:
656 case NVPTX::SUST_B_1D_ARRAY_B8_ZERO_R:
658 case NVPTX::SUST_B_1D_ARRAY_B16_ZERO_R:
660 case NVPTX::SUST_B_1D_ARRAY_B32_ZERO_R:
662 case NVPTX::SUST_B_1D_ARRAY_B64_ZERO_R:
664 case NVPTX::SUST_B_1D_ARRAY_V2B8_ZERO_R:
666 case NVPTX::SUST_B_1D_ARRAY_V2B16_ZERO_R:
668 case NVPTX::SUST_B_1D_ARRAY_V2B32_ZERO_R:
670 case NVPTX::SUST_B_1D_ARRAY_V2B64_ZERO_R:
672 case NVPTX::SUST_B_1D_ARRAY_V4B8_ZERO_R:
674 case NVPTX::SUST_B_1D_ARRAY_V4B16_ZERO_R:
676 case NVPTX::SUST_B_1D_ARRAY_V4B32_ZERO_R:
678 case NVPTX::SUST_B_2D_B8_ZERO_R:
680 case NVPTX::SUST_B_2D_B16_ZERO_R:
682 case NVPTX::SUST_B_2D_B32_ZERO_R:
684 case NVPTX::SUST_B_2D_B64_ZERO_R:
686 case NVPTX::SUST_B_2D_V2B8_ZERO_R:
688 case NVPTX::SUST_B_2D_V2B16_ZERO_R:
690 case NVPTX::SUST_B_2D_V2B32_ZERO_R:
692 case NVPTX::SUST_B_2D_V2B64_ZERO_R:
694 case NVPTX::SUST_B_2D_V4B8_ZERO_R:
696 case NVPTX::SUST_B_2D_V4B16_ZERO_R:
698 case NVPTX::SUST_B_2D_V4B32_ZERO_R:
700 case NVPTX::SUST_B_2D_ARRAY_B8_ZERO_R:
702 case NVPTX::SUST_B_2D_ARRAY_B16_ZERO_R:
704 case NVPTX::SUST_B_2D_ARRAY_B32_ZERO_R:
706 case NVPTX::SUST_B_2D_ARRAY_B64_ZERO_R:
708 case NVPTX::SUST_B_2D_ARRAY_V2B8_ZERO_R:
710 case NVPTX::SUST_B_2D_ARRAY_V2B16_ZERO_R:
712 case NVPTX::SUST_B_2D_ARRAY_V2B32_ZERO_R:
714 case NVPTX::SUST_B_2D_ARRAY_V2B64_ZERO_R:
716 case NVPTX::SUST_B_2D_ARRAY_V4B8_ZERO_R:
718 case NVPTX::SUST_B_2D_ARRAY_V4B16_ZERO_R:
720 case NVPTX::SUST_B_2D_ARRAY_V4B32_ZERO_R:
722 case NVPTX::SUST_B_3D_B8_ZERO_R:
724 case NVPTX::SUST_B_3D_B16_ZERO_R:
726 case NVPTX::SUST_B_3D_B32_ZERO_R:
728 case NVPTX::SUST_B_3D_B64_ZERO_R:
730 case NVPTX::SUST_B_3D_V2B8_ZERO_R:
732 case NVPTX::SUST_B_3D_V2B16_ZERO_R:
734 case NVPTX::SUST_B_3D_V2B32_ZERO_R:
736 case NVPTX::SUST_B_3D_V2B64_ZERO_R:
738 case NVPTX::SUST_B_3D_V4B8_ZERO_R:
740 case NVPTX::SUST_B_3D_V4B16_ZERO_R:
742 case NVPTX::SUST_B_3D_V4B32_ZERO_R:
744 case NVPTX::SUST_P_1D_B8_TRAP_R:
746 case NVPTX::SUST_P_1D_B16_TRAP_R:
748 case NVPTX::SUST_P_1D_B32_TRAP_R:
750 case NVPTX::SUST_P_1D_V2B8_TRAP_R:
752 case NVPTX::SUST_P_1D_V2B16_TRAP_R:
754 case NVPTX::SUST_P_1D_V2B32_TRAP_R:
756 case NVPTX::SUST_P_1D_V4B8_TRAP_R:
758 case NVPTX::SUST_P_1D_V4B16_TRAP_R:
760 case NVPTX::SUST_P_1D_V4B32_TRAP_R:
762 case NVPTX::SUST_P_1D_ARRAY_B8_TRAP_R:
764 case NVPTX::SUST_P_1D_ARRAY_B16_TRAP_R:
766 case NVPTX::SUST_P_1D_ARRAY_B32_TRAP_R:
768 case NVPTX::SUST_P_1D_ARRAY_V2B8_TRAP_R:
770 case NVPTX::SUST_P_1D_ARRAY_V2B16_TRAP_R:
772 case NVPTX::SUST_P_1D_ARRAY_V2B32_TRAP_R:
774 case NVPTX::SUST_P_1D_ARRAY_V4B8_TRAP_R:
776 case NVPTX::SUST_P_1D_ARRAY_V4B16_TRAP_R:
778 case NVPTX::SUST_P_1D_ARRAY_V4B32_TRAP_R:
780 case NVPTX::SUST_P_2D_B8_TRAP_R:
782 case NVPTX::SUST_P_2D_B16_TRAP_R:
784 case NVPTX::SUST_P_2D_B32_TRAP_R:
786 case NVPTX::SUST_P_2D_V2B8_TRAP_R:
788 case NVPTX::SUST_P_2D_V2B16_TRAP_R:
790 case NVPTX::SUST_P_2D_V2B32_TRAP_R:
792 case NVPTX::SUST_P_2D_V4B8_TRAP_R:
794 case NVPTX::SUST_P_2D_V4B16_TRAP_R:
796 case NVPTX::SUST_P_2D_V4B32_TRAP_R:
798 case NVPTX::SUST_P_2D_ARRAY_B8_TRAP_R:
800 case NVPTX::SUST_P_2D_ARRAY_B16_TRAP_R:
802 case NVPTX::SUST_P_2D_ARRAY_B32_TRAP_R:
804 case NVPTX::SUST_P_2D_ARRAY_V2B8_TRAP_R:
806 case NVPTX::SUST_P_2D_ARRAY_V2B16_TRAP_R:
808 case NVPTX::SUST_P_2D_ARRAY_V2B32_TRAP_R:
810 case NVPTX::SUST_P_2D_ARRAY_V4B8_TRAP_R:
812 case NVPTX::SUST_P_2D_ARRAY_V4B16_TRAP_R:
814 case NVPTX::SUST_P_2D_ARRAY_V4B32_TRAP_R:
816 case NVPTX::SUST_P_3D_B8_TRAP_R:
818 case NVPTX::SUST_P_3D_B16_TRAP_R:
820 case NVPTX::SUST_P_3D_B32_TRAP_R:
822 case NVPTX::SUST_P_3D_V2B8_TRAP_R:
824 case NVPTX::SUST_P_3D_V2B16_TRAP_R:
826 case NVPTX::SUST_P_3D_V2B32_TRAP_R:
828 case NVPTX::SUST_P_3D_V4B8_TRAP_R:
830 case NVPTX::SUST_P_3D_V4B16_TRAP_R:
832 case NVPTX::SUST_P_3D_V4B32_TRAP_R:
841 case NVPTX::TEX_1D_F32_S32_RR:
843 case NVPTX::TEX_1D_F32_S32_RI:
845 case NVPTX::TEX_1D_F32_F32_RR:
847 case NVPTX::TEX_1D_F32_F32_RI:
849 case NVPTX::TEX_1D_F32_F32_LEVEL_RR:
851 case NVPTX::TEX_1D_F32_F32_LEVEL_RI:
853 case NVPTX::TEX_1D_F32_F32_GRAD_RR:
855 case NVPTX::TEX_1D_F32_F32_GRAD_RI:
857 case NVPTX::TEX_1D_S32_S32_RR:
859 case NVPTX::TEX_1D_S32_S32_RI:
861 case NVPTX::TEX_1D_S32_F32_RR:
863 case NVPTX::TEX_1D_S32_F32_RI:
865 case NVPTX::TEX_1D_S32_F32_LEVEL_RR:
867 case NVPTX::TEX_1D_S32_F32_LEVEL_RI:
869 case NVPTX::TEX_1D_S32_F32_GRAD_RR:
871 case NVPTX::TEX_1D_S32_F32_GRAD_RI:
873 case NVPTX::TEX_1D_U32_S32_RR:
875 case NVPTX::TEX_1D_U32_S32_RI:
877 case NVPTX::TEX_1D_U32_F32_RR:
879 case NVPTX::TEX_1D_U32_F32_RI:
881 case NVPTX::TEX_1D_U32_F32_LEVEL_RR:
883 case NVPTX::TEX_1D_U32_F32_LEVEL_RI:
885 case NVPTX::TEX_1D_U32_F32_GRAD_RR:
887 case NVPTX::TEX_1D_U32_F32_GRAD_RI:
889 case NVPTX::TEX_1D_ARRAY_F32_S32_RR:
891 case NVPTX::TEX_1D_ARRAY_F32_S32_RI:
893 case NVPTX::TEX_1D_ARRAY_F32_F32_RR:
895 case NVPTX::TEX_1D_ARRAY_F32_F32_RI:
897 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RR:
899 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RI:
901 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RR:
903 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RI:
905 case NVPTX::TEX_1D_ARRAY_S32_S32_RR:
907 case NVPTX::TEX_1D_ARRAY_S32_S32_RI:
909 case NVPTX::TEX_1D_ARRAY_S32_F32_RR:
911 case NVPTX::TEX_1D_ARRAY_S32_F32_RI:
913 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RR:
915 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RI:
917 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RR:
919 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RI:
921 case NVPTX::TEX_1D_ARRAY_U32_S32_RR:
923 case NVPTX::TEX_1D_ARRAY_U32_S32_RI:
925 case NVPTX::TEX_1D_ARRAY_U32_F32_RR:
927 case NVPTX::TEX_1D_ARRAY_U32_F32_RI:
929 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RR:
931 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RI:
933 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RR:
935 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RI:
937 case NVPTX::TEX_2D_F32_S32_RR:
939 case NVPTX::TEX_2D_F32_S32_RI:
941 case NVPTX::TEX_2D_F32_F32_RR:
943 case NVPTX::TEX_2D_F32_F32_RI:
945 case NVPTX::TEX_2D_F32_F32_LEVEL_RR:
947 case NVPTX::TEX_2D_F32_F32_LEVEL_RI:
949 case NVPTX::TEX_2D_F32_F32_GRAD_RR:
951 case NVPTX::TEX_2D_F32_F32_GRAD_RI:
953 case NVPTX::TEX_2D_S32_S32_RR:
955 case NVPTX::TEX_2D_S32_S32_RI:
957 case NVPTX::TEX_2D_S32_F32_RR:
959 case NVPTX::TEX_2D_S32_F32_RI:
961 case NVPTX::TEX_2D_S32_F32_LEVEL_RR:
963 case NVPTX::TEX_2D_S32_F32_LEVEL_RI:
965 case NVPTX::TEX_2D_S32_F32_GRAD_RR:
967 case NVPTX::TEX_2D_S32_F32_GRAD_RI:
969 case NVPTX::TEX_2D_U32_S32_RR:
971 case NVPTX::TEX_2D_U32_S32_RI:
973 case NVPTX::TEX_2D_U32_F32_RR:
975 case NVPTX::TEX_2D_U32_F32_RI:
977 case NVPTX::TEX_2D_U32_F32_LEVEL_RR:
979 case NVPTX::TEX_2D_U32_F32_LEVEL_RI:
981 case NVPTX::TEX_2D_U32_F32_GRAD_RR:
983 case NVPTX::TEX_2D_U32_F32_GRAD_RI:
985 case NVPTX::TEX_2D_ARRAY_F32_S32_RR:
987 case NVPTX::TEX_2D_ARRAY_F32_S32_RI:
989 case NVPTX::TEX_2D_ARRAY_F32_F32_RR:
991 case NVPTX::TEX_2D_ARRAY_F32_F32_RI:
993 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RR:
995 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RI:
997 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RR:
999 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RI:
1001 case NVPTX::TEX_2D_ARRAY_S32_S32_RR:
1003 case NVPTX::TEX_2D_ARRAY_S32_S32_RI:
1005 case NVPTX::TEX_2D_ARRAY_S32_F32_RR:
1007 case NVPTX::TEX_2D_ARRAY_S32_F32_RI:
1009 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RR:
1011 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RI:
1013 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RR:
1015 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RI:
1017 case NVPTX::TEX_2D_ARRAY_U32_S32_RR:
1019 case NVPTX::TEX_2D_ARRAY_U32_S32_RI:
1021 case NVPTX::TEX_2D_ARRAY_U32_F32_RR:
1023 case NVPTX::TEX_2D_ARRAY_U32_F32_RI:
1025 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RR:
1027 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RI:
1029 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RR:
1031 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RI:
1033 case NVPTX::TEX_3D_F32_S32_RR:
1035 case NVPTX::TEX_3D_F32_S32_RI:
1037 case NVPTX::TEX_3D_F32_F32_RR:
1039 case NVPTX::TEX_3D_F32_F32_RI:
1041 case NVPTX::TEX_3D_F32_F32_LEVEL_RR:
1043 case NVPTX::TEX_3D_F32_F32_LEVEL_RI:
1045 case NVPTX::TEX_3D_F32_F32_GRAD_RR:
1047 case NVPTX::TEX_3D_F32_F32_GRAD_RI:
1049 case NVPTX::TEX_3D_S32_S32_RR:
1051 case NVPTX::TEX_3D_S32_S32_RI:
1053 case NVPTX::TEX_3D_S32_F32_RR:
1055 case NVPTX::TEX_3D_S32_F32_RI:
1057 case NVPTX::TEX_3D_S32_F32_LEVEL_RR:
1059 case NVPTX::TEX_3D_S32_F32_LEVEL_RI:
1061 case NVPTX::TEX_3D_S32_F32_GRAD_RR:
1063 case NVPTX::TEX_3D_S32_F32_GRAD_RI:
1065 case NVPTX::TEX_3D_U32_S32_RR:
1067 case NVPTX::TEX_3D_U32_S32_RI:
1069 case NVPTX::TEX_3D_U32_F32_RR:
1071 case NVPTX::TEX_3D_U32_F32_RI:
1073 case NVPTX::TEX_3D_U32_F32_LEVEL_RR:
1075 case NVPTX::TEX_3D_U32_F32_LEVEL_RI:
1077 case NVPTX::TEX_3D_U32_F32_GRAD_RR:
1079 case NVPTX::TEX_3D_U32_F32_GRAD_RI:
1081 case NVPTX::TEX_CUBE_F32_F32_RR:
1083 case NVPTX::TEX_CUBE_F32_F32_RI:
1085 case NVPTX::TEX_CUBE_F32_F32_LEVEL_RR:
1087 case NVPTX::TEX_CUBE_F32_F32_LEVEL_RI:
1089 case NVPTX::TEX_CUBE_S32_F32_RR:
1091 case NVPTX::TEX_CUBE_S32_F32_RI:
1093 case NVPTX::TEX_CUBE_S32_F32_LEVEL_RR:
1095 case NVPTX::TEX_CUBE_S32_F32_LEVEL_RI:
1097 case NVPTX::TEX_CUBE_U32_F32_RR:
1099 case NVPTX::TEX_CUBE_U32_F32_RI:
1101 case NVPTX::TEX_CUBE_U32_F32_LEVEL_RR:
1103 case NVPTX::TEX_CUBE_U32_F32_LEVEL_RI:
1105 case NVPTX::TEX_CUBE_ARRAY_F32_F32_RR:
1107 case NVPTX::TEX_CUBE_ARRAY_F32_F32_RI:
1109 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RR:
1111 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RI:
1113 case NVPTX::TEX_CUBE_ARRAY_S32_F32_RR:
1115 case NVPTX::TEX_CUBE_ARRAY_S32_F32_RI:
1117 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RR:
1119 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RI:
1121 case NVPTX::TEX_CUBE_ARRAY_U32_F32_RR:
1123 case NVPTX::TEX_CUBE_ARRAY_U32_F32_RI:
1125 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RR:
1127 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RI:
1129 case NVPTX::TLD4_R_2D_F32_F32_RR:
1131 case NVPTX::TLD4_R_2D_F32_F32_RI:
1133 case NVPTX::TLD4_G_2D_F32_F32_RR:
1135 case NVPTX::TLD4_G_2D_F32_F32_RI:
1137 case NVPTX::TLD4_B_2D_F32_F32_RR:
1139 case NVPTX::TLD4_B_2D_F32_F32_RI:
1141 case NVPTX::TLD4_A_2D_F32_F32_RR:
1143 case NVPTX::TLD4_A_2D_F32_F32_RI:
1145 case NVPTX::TLD4_R_2D_S32_F32_RR:
1147 case NVPTX::TLD4_R_2D_S32_F32_RI:
1149 case NVPTX::TLD4_G_2D_S32_F32_RR:
1151 case NVPTX::TLD4_G_2D_S32_F32_RI:
1153 case NVPTX::TLD4_B_2D_S32_F32_RR:
1155 case NVPTX::TLD4_B_2D_S32_F32_RI:
1157 case NVPTX::TLD4_A_2D_S32_F32_RR:
1159 case NVPTX::TLD4_A_2D_S32_F32_RI:
1161 case NVPTX::TLD4_R_2D_U32_F32_RR:
1163 case NVPTX::TLD4_R_2D_U32_F32_RI:
1165 case NVPTX::TLD4_G_2D_U32_F32_RR:
1167 case NVPTX::TLD4_G_2D_U32_F32_RI:
1169 case NVPTX::TLD4_B_2D_U32_F32_RR:
1171 case NVPTX::TLD4_B_2D_U32_F32_RI:
1173 case NVPTX::TLD4_A_2D_U32_F32_RR:
1175 case NVPTX::TLD4_A_2D_U32_F32_RI:
1177 case NVPTX::TEX_UNIFIED_1D_F32_S32_R:
1179 case NVPTX::TEX_UNIFIED_1D_F32_F32_R:
1181 case NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL_R:
1183 case NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD_R:
1185 case NVPTX::TEX_UNIFIED_1D_S32_S32_R:
1187 case NVPTX::TEX_UNIFIED_1D_S32_F32_R:
1189 case NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL_R:
1191 case NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD_R:
1193 case NVPTX::TEX_UNIFIED_1D_U32_S32_R:
1195 case NVPTX::TEX_UNIFIED_1D_U32_F32_R:
1197 case NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL_R:
1199 case NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD_R:
1201 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32_R:
1203 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_R:
1205 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL_R:
1207 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD_R:
1209 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32_R:
1211 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_R:
1213 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL_R:
1215 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD_R:
1217 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32_R:
1219 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_R:
1221 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL_R:
1223 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD_R:
1225 case NVPTX::TEX_UNIFIED_2D_F32_S32_R:
1227 case NVPTX::TEX_UNIFIED_2D_F32_F32_R:
1229 case NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL_R:
1231 case NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD_R:
1233 case NVPTX::TEX_UNIFIED_2D_S32_S32_R:
1235 case NVPTX::TEX_UNIFIED_2D_S32_F32_R:
1237 case NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL_R:
1239 case NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD_R:
1241 case NVPTX::TEX_UNIFIED_2D_U32_S32_R:
1243 case NVPTX::TEX_UNIFIED_2D_U32_F32_R:
1245 case NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL_R:
1247 case NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD_R:
1249 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32_R:
1251 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_R:
1253 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL_R:
1255 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD_R:
1257 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32_R:
1259 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_R:
1261 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL_R:
1263 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD_R:
1265 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32_R:
1267 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_R:
1269 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL_R:
1271 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD_R:
1273 case NVPTX::TEX_UNIFIED_3D_F32_S32_R:
1275 case NVPTX::TEX_UNIFIED_3D_F32_F32_R:
1277 case NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL_R:
1279 case NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD_R:
1281 case NVPTX::TEX_UNIFIED_3D_S32_S32_R:
1283 case NVPTX::TEX_UNIFIED_3D_S32_F32_R:
1285 case NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL_R:
1287 case NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD_R:
1289 case NVPTX::TEX_UNIFIED_3D_U32_S32_R:
1291 case NVPTX::TEX_UNIFIED_3D_U32_F32_R:
1293 case NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL_R:
1295 case NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD_R:
1297 case NVPTX::TEX_UNIFIED_CUBE_F32_F32_R:
1299 case NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL_R:
1301 case NVPTX::TEX_UNIFIED_CUBE_S32_F32_R:
1303 case NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL_R:
1305 case NVPTX::TEX_UNIFIED_CUBE_U32_F32_R:
1307 case NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL_R:
1309 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_R:
1311 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL_R:
1313 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_R:
1315 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL_R:
1317 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_R:
1319 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_R:
1321 case NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_R:
1323 case NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_R:
1325 case NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_R:
1327 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R:
1329 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R:
1331 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R:
1333 case NVPTX::TLD4_UNIFIED_R_2D_F32_F32_R:
1335 case NVPTX::TLD4_UNIFIED_G_2D_F32_F32_R:
1337 case NVPTX::TLD4_UNIFIED_B_2D_F32_F32_R:
1339 case NVPTX::TLD4_UNIFIED_A_2D_F32_F32_R:
1341 case NVPTX::TLD4_UNIFIED_R_2D_S32_F32_R:
1343 case NVPTX::TLD4_UNIFIED_G_2D_S32_F32_R:
1345 case NVPTX::TLD4_UNIFIED_B_2D_S32_F32_R:
1347 case NVPTX::TLD4_UNIFIED_A_2D_S32_F32_R:
1349 case NVPTX::TLD4_UNIFIED_R_2D_U32_F32_R:
1351 case NVPTX::TLD4_UNIFIED_G_2D_U32_F32_R:
1353 case NVPTX::TLD4_UNIFIED_B_2D_U32_F32_R:
1355 case NVPTX::TLD4_UNIFIED_A_2D_U32_F32_R:
1364 case NVPTX::TEX_1D_F32_S32_RR:
1366 case NVPTX::TEX_1D_F32_S32_IR:
1368 case NVPTX::TEX_1D_F32_F32_RR:
1370 case NVPTX::TEX_1D_F32_F32_IR:
1372 case NVPTX::TEX_1D_F32_F32_LEVEL_RR:
1374 case NVPTX::TEX_1D_F32_F32_LEVEL_IR:
1376 case NVPTX::TEX_1D_F32_F32_GRAD_RR:
1378 case NVPTX::TEX_1D_F32_F32_GRAD_IR:
1380 case NVPTX::TEX_1D_S32_S32_RR:
1382 case NVPTX::TEX_1D_S32_S32_IR:
1384 case NVPTX::TEX_1D_S32_F32_RR:
1386 case NVPTX::TEX_1D_S32_F32_IR:
1388 case NVPTX::TEX_1D_S32_F32_LEVEL_RR:
1390 case NVPTX::TEX_1D_S32_F32_LEVEL_IR:
1392 case NVPTX::TEX_1D_S32_F32_GRAD_RR:
1394 case NVPTX::TEX_1D_S32_F32_GRAD_IR:
1396 case NVPTX::TEX_1D_U32_S32_RR:
1398 case NVPTX::TEX_1D_U32_S32_IR:
1400 case NVPTX::TEX_1D_U32_F32_RR:
1402 case NVPTX::TEX_1D_U32_F32_IR:
1404 case NVPTX::TEX_1D_U32_F32_LEVEL_RR:
1406 case NVPTX::TEX_1D_U32_F32_LEVEL_IR:
1408 case NVPTX::TEX_1D_U32_F32_GRAD_RR:
1410 case NVPTX::TEX_1D_U32_F32_GRAD_IR:
1412 case NVPTX::TEX_1D_ARRAY_F32_S32_RR:
1414 case NVPTX::TEX_1D_ARRAY_F32_S32_IR:
1416 case NVPTX::TEX_1D_ARRAY_F32_F32_RR:
1418 case NVPTX::TEX_1D_ARRAY_F32_F32_IR:
1420 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RR:
1422 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_IR:
1424 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RR:
1426 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_IR:
1428 case NVPTX::TEX_1D_ARRAY_S32_S32_RR:
1430 case NVPTX::TEX_1D_ARRAY_S32_S32_IR:
1432 case NVPTX::TEX_1D_ARRAY_S32_F32_RR:
1434 case NVPTX::TEX_1D_ARRAY_S32_F32_IR:
1436 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RR:
1438 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_IR:
1440 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RR:
1442 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_IR:
1444 case NVPTX::TEX_1D_ARRAY_U32_S32_RR:
1446 case NVPTX::TEX_1D_ARRAY_U32_S32_IR:
1448 case NVPTX::TEX_1D_ARRAY_U32_F32_RR:
1450 case NVPTX::TEX_1D_ARRAY_U32_F32_IR:
1452 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RR:
1454 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_IR:
1456 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RR:
1458 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_IR:
1460 case NVPTX::TEX_2D_F32_S32_RR:
1462 case NVPTX::TEX_2D_F32_S32_IR:
1464 case NVPTX::TEX_2D_F32_F32_RR:
1466 case NVPTX::TEX_2D_F32_F32_IR:
1468 case NVPTX::TEX_2D_F32_F32_LEVEL_RR:
1470 case NVPTX::TEX_2D_F32_F32_LEVEL_IR:
1472 case NVPTX::TEX_2D_F32_F32_GRAD_RR:
1474 case NVPTX::TEX_2D_F32_F32_GRAD_IR:
1476 case NVPTX::TEX_2D_S32_S32_RR:
1478 case NVPTX::TEX_2D_S32_S32_IR:
1480 case NVPTX::TEX_2D_S32_F32_RR:
1482 case NVPTX::TEX_2D_S32_F32_IR:
1484 case NVPTX::TEX_2D_S32_F32_LEVEL_RR:
1486 case NVPTX::TEX_2D_S32_F32_LEVEL_IR:
1488 case NVPTX::TEX_2D_S32_F32_GRAD_RR:
1490 case NVPTX::TEX_2D_S32_F32_GRAD_IR:
1492 case NVPTX::TEX_2D_U32_S32_RR:
1494 case NVPTX::TEX_2D_U32_S32_IR:
1496 case NVPTX::TEX_2D_U32_F32_RR:
1498 case NVPTX::TEX_2D_U32_F32_IR:
1500 case NVPTX::TEX_2D_U32_F32_LEVEL_RR:
1502 case NVPTX::TEX_2D_U32_F32_LEVEL_IR:
1504 case NVPTX::TEX_2D_U32_F32_GRAD_RR:
1506 case NVPTX::TEX_2D_U32_F32_GRAD_IR:
1508 case NVPTX::TEX_2D_ARRAY_F32_S32_RR:
1510 case NVPTX::TEX_2D_ARRAY_F32_S32_IR:
1512 case NVPTX::TEX_2D_ARRAY_F32_F32_RR:
1514 case NVPTX::TEX_2D_ARRAY_F32_F32_IR:
1516 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RR:
1518 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_IR:
1520 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RR:
1522 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_IR:
1524 case NVPTX::TEX_2D_ARRAY_S32_S32_RR:
1526 case NVPTX::TEX_2D_ARRAY_S32_S32_IR:
1528 case NVPTX::TEX_2D_ARRAY_S32_F32_RR:
1530 case NVPTX::TEX_2D_ARRAY_S32_F32_IR:
1532 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RR:
1534 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_IR:
1536 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RR:
1538 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_IR:
1540 case NVPTX::TEX_2D_ARRAY_U32_S32_RR:
1542 case NVPTX::TEX_2D_ARRAY_U32_S32_IR:
1544 case NVPTX::TEX_2D_ARRAY_U32_F32_RR:
1546 case NVPTX::TEX_2D_ARRAY_U32_F32_IR:
1548 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RR:
1550 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_IR:
1552 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RR:
1554 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_IR:
1556 case NVPTX::TEX_3D_F32_S32_RR:
1558 case NVPTX::TEX_3D_F32_S32_IR:
1560 case NVPTX::TEX_3D_F32_F32_RR:
1562 case NVPTX::TEX_3D_F32_F32_IR:
1564 case NVPTX::TEX_3D_F32_F32_LEVEL_RR:
1566 case NVPTX::TEX_3D_F32_F32_LEVEL_IR:
1568 case NVPTX::TEX_3D_F32_F32_GRAD_RR:
1570 case NVPTX::TEX_3D_F32_F32_GRAD_IR:
1572 case NVPTX::TEX_3D_S32_S32_RR:
1574 case NVPTX::TEX_3D_S32_S32_IR:
1576 case NVPTX::TEX_3D_S32_F32_RR:
1578 case NVPTX::TEX_3D_S32_F32_IR:
1580 case NVPTX::TEX_3D_S32_F32_LEVEL_RR:
1582 case NVPTX::TEX_3D_S32_F32_LEVEL_IR:
1584 case NVPTX::TEX_3D_S32_F32_GRAD_RR:
1586 case NVPTX::TEX_3D_S32_F32_GRAD_IR:
1588 case NVPTX::TEX_3D_U32_S32_RR:
1590 case NVPTX::TEX_3D_U32_S32_IR:
1592 case NVPTX::TEX_3D_U32_F32_RR:
1594 case NVPTX::TEX_3D_U32_F32_IR:
1596 case NVPTX::TEX_3D_U32_F32_LEVEL_RR:
1598 case NVPTX::TEX_3D_U32_F32_LEVEL_IR:
1600 case NVPTX::TEX_3D_U32_F32_GRAD_RR:
1602 case NVPTX::TEX_3D_U32_F32_GRAD_IR:
1604 case NVPTX::TEX_CUBE_F32_F32_RR:
1606 case NVPTX::TEX_CUBE_F32_F32_IR:
1608 case NVPTX::TEX_CUBE_F32_F32_LEVEL_RR:
1610 case NVPTX::TEX_CUBE_F32_F32_LEVEL_IR:
1612 case NVPTX::TEX_CUBE_S32_F32_RR:
1614 case NVPTX::TEX_CUBE_S32_F32_IR:
1616 case NVPTX::TEX_CUBE_S32_F32_LEVEL_RR:
1618 case NVPTX::TEX_CUBE_S32_F32_LEVEL_IR:
1620 case NVPTX::TEX_CUBE_U32_F32_RR:
1622 case NVPTX::TEX_CUBE_U32_F32_IR:
1624 case NVPTX::TEX_CUBE_U32_F32_LEVEL_RR:
1626 case NVPTX::TEX_CUBE_U32_F32_LEVEL_IR:
1628 case NVPTX::TEX_CUBE_ARRAY_F32_F32_RR:
1630 case NVPTX::TEX_CUBE_ARRAY_F32_F32_IR:
1632 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RR:
1634 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_IR:
1636 case NVPTX::TEX_CUBE_ARRAY_S32_F32_RR:
1638 case NVPTX::TEX_CUBE_ARRAY_S32_F32_IR:
1640 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RR:
1642 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_IR:
1644 case NVPTX::TEX_CUBE_ARRAY_U32_F32_RR:
1646 case NVPTX::TEX_CUBE_ARRAY_U32_F32_IR:
1648 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RR:
1650 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_IR:
1652 case NVPTX::TLD4_R_2D_F32_F32_RR:
1654 case NVPTX::TLD4_R_2D_F32_F32_IR:
1656 case NVPTX::TLD4_G_2D_F32_F32_RR:
1658 case NVPTX::TLD4_G_2D_F32_F32_IR:
1660 case NVPTX::TLD4_B_2D_F32_F32_RR:
1662 case NVPTX::TLD4_B_2D_F32_F32_IR:
1664 case NVPTX::TLD4_A_2D_F32_F32_RR:
1666 case NVPTX::TLD4_A_2D_F32_F32_IR:
1668 case NVPTX::TLD4_R_2D_S32_F32_RR:
1670 case NVPTX::TLD4_R_2D_S32_F32_IR:
1672 case NVPTX::TLD4_G_2D_S32_F32_RR:
1674 case NVPTX::TLD4_G_2D_S32_F32_IR:
1676 case NVPTX::TLD4_B_2D_S32_F32_RR:
1678 case NVPTX::TLD4_B_2D_S32_F32_IR:
1680 case NVPTX::TLD4_A_2D_S32_F32_RR:
1682 case NVPTX::TLD4_A_2D_S32_F32_IR:
1684 case NVPTX::TLD4_R_2D_U32_F32_RR:
1686 case NVPTX::TLD4_R_2D_U32_F32_IR:
1688 case NVPTX::TLD4_G_2D_U32_F32_RR:
1690 case NVPTX::TLD4_G_2D_U32_F32_IR:
1692 case NVPTX::TLD4_B_2D_U32_F32_RR:
1694 case NVPTX::TLD4_B_2D_U32_F32_IR:
1696 case NVPTX::TLD4_A_2D_U32_F32_RR:
1698 case NVPTX::TLD4_A_2D_U32_F32_IR:
1707 case NVPTX::TXQ_CHANNEL_ORDER_R:
1709 case NVPTX::TXQ_CHANNEL_DATA_TYPE_R:
1711 case NVPTX::TXQ_WIDTH_R:
1713 case NVPTX::TXQ_HEIGHT_R:
1715 case NVPTX::TXQ_DEPTH_R:
1717 case NVPTX::TXQ_ARRAY_SIZE_R:
1719 case NVPTX::TXQ_NUM_SAMPLES_R:
1721 case NVPTX::TXQ_NUM_MIPMAP_LEVELS_R:
1723 case NVPTX::SUQ_CHANNEL_ORDER_R:
1725 case NVPTX::SUQ_CHANNEL_DATA_TYPE_R:
1727 case NVPTX::SUQ_WIDTH_R:
1729 case NVPTX::SUQ_HEIGHT_R:
1731 case NVPTX::SUQ_DEPTH_R:
1733 case NVPTX::SUQ_ARRAY_SIZE_R:
1812 case NVPTX::LD_i64_avar: {
1836 case NVPTX::texsurf_handles: {
1845 case NVPTX::nvvm_move_i64:
1846 case TargetOpcode::COPY: {