Lines Matching defs:Ordering

373   NVPTX::Ordering InstructionOrdering, FenceOrdering;
374   OperationOrderings(NVPTX::Ordering IO = NVPTX::Ordering::NotAtomic,
375                      NVPTX::Ordering FO = NVPTX::Ordering::NotAtomic)
381   AtomicOrdering Ordering = N->getSuccessOrdering();
473     return NVPTX::Ordering::NotAtomic;
476   // [2]: Atomics with Ordering different than Unordered or Relaxed are not
478   if (!(Ordering == AtomicOrdering::NotAtomic ||
479         Ordering == AtomicOrdering::Unordered ||
480         Ordering == AtomicOrdering::Monotonic) &&
486                 toIRString(Ordering)));
501     return NVPTX::Ordering::NotAtomic;
506   switch (Ordering) {
508     return N->isVolatile() ? NVPTX::Ordering::Volatile
509                            : NVPTX::Ordering::NotAtomic;
515       return UseRelaxedMMIO ? NVPTX::Ordering::RelaxedMMIO
516                             : NVPTX::Ordering::Volatile;
518       return HasMemoryOrdering ? NVPTX::Ordering::Relaxed
519                                : NVPTX::Ordering::Volatile;
525           formatv("PTX only supports Acquire Ordering on reads: {}",
527     return NVPTX::Ordering::Acquire;
531           formatv("PTX only supports Release Ordering on writes: {}",
533     return NVPTX::Ordering::Release;
536         formatv("NVPTX does not support AcquireRelease Ordering on "
544     // Ordering that differs from "sc": acq, rel, or acq_rel, depending on
549     NVPTX::Ordering InstrOrder;
551       InstrOrder = NVPTX::Ordering::Acquire;
553       InstrOrder = NVPTX::Ordering::Release;
556           formatv("NVPTX does not support SequentiallyConsistent Ordering on "
560                               NVPTX::Ordering::SequentiallyConsistent);
565               toIRString(Ordering)));
571                                                   NVPTX::Ordering O) const {
573   case NVPTX::Ordering::NotAtomic:
574   case NVPTX::Ordering::Volatile: // Non-atomic volatile operations
577   case NVPTX::Ordering::RelaxedMMIO:
582   case NVPTX::Ordering::Relaxed:
583   case NVPTX::Ordering::Acquire:
584   case NVPTX::Ordering::Release:
585   case NVPTX::Ordering::AcquireRelease:
586   case NVPTX::Ordering::SequentiallyConsistent:
646 static unsigned int getFenceOp(NVPTX::Ordering O, NVPTX::Scope S,
652   case NVPTX::Ordering::Acquire:
653   case NVPTX::Ordering::Release:
654   case NVPTX::Ordering::AcquireRelease: {
674   case NVPTX::Ordering::SequentiallyConsistent: {
693   case NVPTX::Ordering::NotAtomic:
694   case NVPTX::Ordering::Relaxed:
695   case NVPTX::Ordering::Volatile:
696   case NVPTX::Ordering::RelaxedMMIO:
707 std::pair<NVPTX::Ordering, NVPTX::Scope>
715   switch (NVPTX::Ordering(FenceOrdering)) {
716   case NVPTX::Ordering::NotAtomic:
718   case NVPTX::Ordering::SequentiallyConsistent: {
726                 OrderingToString(NVPTX::Ordering(FenceOrdering))));
897   auto [Ordering, Scope] = insertMemoryInstructionFence(DL, Chain, LD);
932   SmallVector<SDValue, 12> Ops({getI32Imm(Ordering, DL), getI32Imm(Scope, DL),
1020   auto [Ordering, Scope] = insertMemoryInstructionFence(DL, Chain, MemSD);
1069   SmallVector<SDValue, 12> Ops({getI32Imm(Ordering, DL), getI32Imm(Scope, DL),
1599   auto [Ordering, Scope] = insertMemoryInstructionFence(DL, Chain, ST);
1628       {Value, getI32Imm(Ordering, DL), getI32Imm(Scope, DL),
1709   auto [Ordering, Scope] = insertMemoryInstructionFence(DL, Chain, MemSD);
1744   Ops.append({getI32Imm(Ordering, DL), getI32Imm(Scope, DL),
2795       getFenceOp(NVPTX::Ordering(N->getConstantOperandVal(1)),