Lines Matching defs:Ws

2711   SDValue Ws;
2727     Ws = Op->getOperand(0);
2729     Ws = Op->getOperand(1);
2733   return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2757   SDValue Ws;
2773     Ws = Op->getOperand(0);
2775     Ws = Op->getOperand(1);
2779   return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Ws, Wt);
2804   SDValue Ws;
2820     Ws = Op->getOperand(0);
2822     Ws = Op->getOperand(1);
2826   return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2852   SDValue Ws;
2868     Ws = Op->getOperand(0);
2871     Ws = Op->getOperand(1);
2875   return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2899   SDValue Ws;
2912     Ws = Op->getOperand(0);
2914     Ws = Op->getOperand(1);
2918   return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2942   SDValue Ws;
2955     Ws = Op->getOperand(0);
2957     Ws = Op->getOperand(1);
2961   return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
3230   Register Ws = MI.getOperand(1).getReg();
3234     unsigned Wt = Ws;
3240       BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3249     BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3275   Register Ws = MI.getOperand(1).getReg();
3280     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3284     BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3569   Register Ws = MI.getOperand(0).getReg();
3584   BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3774 //        / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3824   Register Ws = MI.getOperand(1).getReg();
3837   BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);