Lines Matching defs:ResTy
449 EVT ResTy = Op->getValueType(0);
456 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
1404 EVT ResTy = Op->getValueType(0);
1407 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1548 EVT ResTy = Op->getValueType(0);
1551 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1554 SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1556 return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1560 EVT ResTy = Op->getValueType(0);
1562 SDValue One = DAG.getConstant(1, DL, ResTy);
1563 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1565 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1566 DAG.getNOT(DL, Bit, ResTy));
1571 EVT ResTy = Op->getValueType(0);
1572 APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1574 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1576 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1920 EVT ResTy = Op->getValueType(0);
1921 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1924 // If ResTy is v2i64 then the type legalizer will break this node down into
1926 return DAG.getBuildVector(ResTy, DL, Ops);
1931 EVT ResTy = Op->getValueType(0);
1933 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1934 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
2030 EVT ResTy = Op->getValueType(0);
2031 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2032 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
2039 EVT ResTy = Op->getValueType(0);
2040 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2041 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2114 EVT ResTy = Op->getValueType(0);
2115 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2116 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2338 EVT ResTy = Op->getValueType(0);
2348 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2451 EVT ResTy = Op->getValueType(0);
2458 if (ResTy.isInteger()) {
2461 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2501 EVT ResTy = Op->getValueType(0);
2507 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2521 if (ResTy.isInteger() && !HasAnyUndefs)
2547 if (ViaVecTy != ResTy)
2548 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2557 EVT ResTy = Node->getValueType(0);
2559 assert(ResTy.isVector());
2561 unsigned NumElts = ResTy.getVectorNumElements();
2562 SDValue Vector = DAG.getUNDEF(ResTy);
2564 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2592 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2637 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2673 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2705 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2733 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2751 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2779 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Ws, Wt);
2798 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2826 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2845 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2875 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2893 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2918 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2936 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2961 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2977 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2984 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2989 int ResTyNumElts = ResTy.getVectorNumElements();
3034 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
3042 EVT ResTy = Op->getValueType(0);
3044 if (!ResTy.is128BitVector())
3047 int ResTyNumElts = ResTy.getVectorNumElements();
3055 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
3056 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, true, DAG);
3058 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
3060 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
3062 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
3064 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
3066 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
3068 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
3070 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
3072 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, false, DAG);