MipsInstructionSelector.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/Mips/MipsInstructionSelector.cpp

Lines Matching defs:RBI
36                           const MipsRegisterBankInfo &RBI);
63   const MipsRegisterBankInfo &RBI;
82     const MipsRegisterBankInfo &RBI)
84       RBI(RBI),
97   return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
102   return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
112   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
152     return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
158     return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
165     return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
173   if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
175   if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
267   if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
282   if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
306     if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
330     if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
336     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
372     if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
380     if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
391     if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
402       if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
409     if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
430     return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
517     if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
524     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
556     if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI))
563     if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI))
600       if (!MTC1.constrainAllUses(TII, TRI, RBI))
615       if (!PairF64.constrainAllUses(TII, TRI, RBI))
649     if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
655     if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
680       if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI))
693         if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
703       if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
712       if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
809       if (!MIB.constrainAllUses(TII, TRI, RBI))
880     if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI))
888     if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
908     if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
915     if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
926   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
933                               const MipsRegisterBankInfo &RBI) {
934   return new MipsInstructionSelector(TM, Subtarget, RBI);