Lines Matching defs:MipsTargetLowering
98 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
110 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
119 return MipsTargetLowering::getNumRegisters(Context, VT);
122 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
137 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
143 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
149 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
155 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
161 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
167 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
174 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
296 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
541 const MipsTargetLowering *
542 MipsTargetLowering::create(const MipsTargetMachine &TM,
552 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
571 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
1213 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1243 bool MipsTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
1247 bool MipsTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
1251 bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
1261 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
1275 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1281 SDValue MipsTargetLowering::
1361 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1534 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1690 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1720 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1912 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1968 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
2092 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2115 SDValue MipsTargetLowering::
2129 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2143 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2198 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2210 SDValue MipsTargetLowering::
2292 SDValue MipsTargetLowering::
2305 SDValue MipsTargetLowering::
2328 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2343 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2499 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2506 SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG,
2546 SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG,
2570 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2577 SDValue MipsTargetLowering::lowerFCANONICALIZE(SDValue Op,
2591 SDValue MipsTargetLowering::
2609 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2636 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2660 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2670 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2702 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2772 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2898 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2911 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2922 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
3101 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
3105 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
3112 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3130 void MipsTargetLowering::
3188 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3248 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3594 SDValue MipsTargetLowering::LowerCallResult(
3721 SDValue MipsTargetLowering::LowerFormalArguments(
3879 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3888 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(Type *Ty,
3897 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3909 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
4017 MipsTargetLowering::ConstraintType
4018 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
4055 MipsTargetLowering::getSingleConstraintMatchWeight(
4128 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
4135 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4213 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4286 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4381 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4404 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4409 EVT MipsTargetLowering::getOptimalMemOpType(
4417 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4426 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4435 bool MipsTargetLowering::useSoftFloat() const {
4439 void MipsTargetLowering::copyByValRegs(
4492 void MipsTargetLowering::passByValArg(
4588 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4635 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4680 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4759 MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4837 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
4858 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
4904 MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI,
4988 MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI,
5038 MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI,