Lines Matching defs:TmpReg
2792 unsigned TmpReg = DstReg;
2800 TmpReg = ATReg;
2820 unsigned TmpReg = DstReg;
2822 TmpReg = getATReg(IDLoc);
2823 if (!TmpReg)
2827 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2829 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
2842 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2843 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
2845 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2851 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2852 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
2854 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2856 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2860 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
2862 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2864 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2883 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2884 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
2887 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2899 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
2910 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2911 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
2921 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2924 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
3035 unsigned TmpReg = DstReg;
3044 TmpReg = ATReg;
3065 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc,
3067 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg,
3069 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg,
3073 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3079 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
3136 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg,
3140 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3144 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
3268 unsigned TmpReg = DstReg;
3276 TmpReg = ATReg;
3279 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3280 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3284 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3287 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
3462 unsigned TmpReg = Mips::ZERO;
3464 TmpReg = getATReg(IDLoc);
3465 if (!TmpReg)
3470 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,
3473 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
3496 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),
3547 unsigned TmpReg = getATReg(IDLoc);
3548 if (!TmpReg)
3554 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3558 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
3560 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
3561 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
3579 unsigned TmpReg = Mips::ZERO;
3581 TmpReg = getATReg(IDLoc);
3582 if (!TmpReg)
3589 if (TmpReg != Mips::ZERO &&
3590 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
3593 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
3597 if (TmpReg != Mips::ZERO &&
3598 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false,
3604 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
3606 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
3633 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,
3766 unsigned TmpReg = DstReg;
3778 TmpReg = getATReg(IDLoc);
3779 if (!TmpReg)
3785 TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI);
3787 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI);
3803 if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
3809 TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg,
3810 TmpReg, BaseReg, IDLoc, STI);
3833 loadAndAddSymbolAddress(Res.getSymA(), TmpReg, BaseReg,
3854 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI);
3855 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI);
3856 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
3857 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI);
3858 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
3860 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
3863 // Generate the base address in TmpReg.
3864 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
3866 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
3893 unsigned TmpReg = DstReg;
3905 TmpReg = getATReg(IDLoc);
3906 if (!TmpReg)
3912 TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI);
3914 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, MCOperand::createImm(0),
3919 loadImmediate(OffsetOp.getImm(), TmpReg, BaseReg, !ABI.ArePtrs64bit(), true,
3926 loadAndAddSymbolAddress(OffsetOp.getExpr(), TmpReg, BaseReg,
4575 unsigned TmpReg = SrcReg;
4578 TmpReg = getATReg(IDLoc);
4579 if (!TmpReg)
4584 if (loadImmediate(OffsetValue, TmpReg, SrcReg, !ABI.ArePtrs64bit(), true,
4590 std::swap(DstReg, TmpReg);
4594 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI);
4595 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);
4598 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4936 unsigned TmpReg = DReg;
4943 TmpReg = getATReg(Inst.getLoc());
4944 if (!TmpReg)
4949 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4950 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
5061 unsigned TmpReg = DReg;
5067 if (TmpReg == SReg) {
5068 TmpReg = getATReg(Inst.getLoc());
5069 if (!TmpReg)
5074 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
5075 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
5256 unsigned TmpReg = Inst.getOperand(2).getReg();
5263 SrcReg, TmpReg, IDLoc, STI);
5298 unsigned TmpReg = Inst.getOperand(2).getReg();
5305 SrcReg, TmpReg, IDLoc, STI);
5333 unsigned TmpReg = Inst.getOperand(2).getReg();
5335 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
6880 unsigned TmpReg = PrevReg + 1;
6881 while (TmpReg <= RegNo) {
6882 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) ||
6883 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) &&
6887 PrevReg = TmpReg;
6888 Regs.push_back(TmpReg++);
7850 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
7851 ParseStatus Res = parseAnyRegister(TmpReg);
7857 MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
7864 TmpReg.clear();
7869 Res = parseAnyRegister(TmpReg);
7884 MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
8742 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
8743 ParseStatus Res = parseAnyRegister(TmpReg);
8749 MipsOperand &StackRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
8786 TmpReg.clear();
8787 Res = parseAnyRegister(TmpReg);
8793 MipsOperand &ReturnRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);