Lines Matching defs:IDLoc
176 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
220 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
224 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
228 bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
232 unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
235 bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
237 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
240 bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
242 bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
244 bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
246 bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
251 SMLoc IDLoc, MCStreamer &Out,
254 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
257 void expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
259 void expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
262 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
265 bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
268 bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
271 bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
274 bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
278 bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
281 bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
284 bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
287 bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
290 bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
293 bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
296 bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
299 bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
302 bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
305 bool expandRotation(MCInst &Inst, SMLoc IDLoc,
307 bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
309 bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
311 bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
314 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
317 bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
320 bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
323 bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
326 bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
329 bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
332 bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
335 bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
338 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
341 bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
344 bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
347 bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
350 bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
440 bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
1871 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
1879 Inst.setLoc(IDLoc);
1903 return Error(IDLoc, "branch target out of range");
1906 return Error(IDLoc, "branch to misaligned address");
1933 return Error(IDLoc, "branch target out of range");
1936 return Error(IDLoc, "branch to misaligned address");
1949 return Error(IDLoc, "branch target out of range");
1951 return Error(IDLoc, "branch to misaligned address");
1962 return Error(IDLoc, "branch target out of range");
1964 return Error(IDLoc, "branch to misaligned address");
1973 return Error(IDLoc, "branch target out of range");
1975 return Error(IDLoc, "branch to misaligned address");
1986 return Error(IDLoc, "branch target out of range");
1988 return Error(IDLoc, "branch to misaligned address");
1997 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
2017 return Error(IDLoc, "expected immediate operand kind");
2021 return Error(IDLoc, "immediate operand value out of range");
2034 return Error(IDLoc, "expected immediate operand kind");
2037 return Error(IDLoc, "immediate operand value out of range");
2061 Warning(IDLoc, "dividing zero by zero");
2063 Warning(IDLoc, "division by zero");
2089 Warning(IDLoc, "dividing zero by zero");
2091 Warning(IDLoc, "division by zero");
2109 warnIfNoMacro(IDLoc);
2112 return Error(IDLoc, "unsupported constant in relocation");
2120 return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode");
2127 !isGP64bit(), IDLoc, Out, STI))
2146 getContext(), IDLoc);
2150 RelocJalrExpr, IDLoc, *STI);
2164 expandMem9Inst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2167 expandMem16Inst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2193 IDLoc, STI);
2212 return Error(IDLoc, "expected immediate operand kind");
2216 return Error(IDLoc, "immediate operand value out of range");
2222 return Error(IDLoc, "expected immediate operand kind");
2225 return Error(IDLoc, "immediate operand value out of range");
2230 return Error(IDLoc, "expected immediate operand kind");
2233 return Error(IDLoc, "immediate operand value out of range");
2238 return Error(IDLoc, "expected immediate operand kind");
2242 return Error(IDLoc, "immediate operand value out of range");
2247 return Error(IDLoc, "expected immediate operand kind");
2252 return Error(IDLoc, "immediate operand value out of range");
2257 return Error(IDLoc, "expected immediate operand kind");
2260 return Error(IDLoc, "immediate operand value out of range");
2266 return Error(IDLoc, "expected immediate operand kind");
2269 return Error(IDLoc, "immediate operand value out of range");
2276 return Error(IDLoc, "expected immediate operand kind");
2279 return Error(IDLoc, "immediate operand value out of range");
2286 return Error(IDLoc, "expected immediate operand kind");
2289 return Error(IDLoc, "immediate operand value out of range");
2294 return Error(IDLoc, "expected immediate operand kind");
2297 return Error(IDLoc, "immediate operand value out of range");
2302 return Error(IDLoc, "invalid operand for instruction");
2317 return Error(IDLoc, "invalid operand for instruction");
2337 TOut.emitEmptyDelaySlot(false, IDLoc, STI);
2363 tryExpandInstruction(Inst, IDLoc, Out, STI);
2403 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
2415 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc,
2419 TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
2421 Warning(IDLoc, "no .cprestore used in PIC mode");
2429 SMLoc IDLoc = SMLoc();
2432 TOut.emitEmptyDelaySlot(false, IDLoc, STI);
2439 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
2445 return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2447 return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2456 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
2469 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
2475 return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail
2479 return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail
2483 return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2488 return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2521 return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2526 return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail
2532 return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail
2538 return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail
2544 return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail
2547 return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail
2550 return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail
2553 return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail
2557 return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail
2560 return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail
2563 return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail
2566 return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail
2569 return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail
2573 return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2575 return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2577 return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2580 return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2583 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2586 return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2591 return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2596 return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2599 return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2604 return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2610 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2616 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2626 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
2638 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
2644 return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2647 return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2650 return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2653 return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2655 return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2658 return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2661 return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2664 return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2666 return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2669 return expandLoadStoreDMacro(Inst, IDLoc, Out, STI,
2674 return expandStoreDM1Macro(Inst, IDLoc, Out, STI)
2678 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2680 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2682 return expandSne(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2684 return expandSneI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2694 return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2697 return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2701 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
2708 JalrInst.setLoc(IDLoc);
2741 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc,
2761 /// @param IDLoc Location of the immediate in the source file.
2764 bool IsAddress, SMLoc IDLoc, MCStreamer &Out,
2769 Error(IDLoc, "instruction requires a 64-bit architecture");
2780 Error(IDLoc, "instruction requires a 32-bit immediate");
2797 unsigned ATReg = getATReg(IDLoc);
2811 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2815 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2822 TmpReg = getATReg(IDLoc);
2827 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2829 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
2834 warnIfNoMacro(IDLoc);
2842 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2843 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
2845 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2851 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2852 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
2854 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2856 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2860 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
2862 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2864 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2870 Error(IDLoc, "instruction requires a 32-bit immediate");
2883 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2884 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
2887 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2892 warnIfNoMacro(IDLoc);
2900 IDLoc, Out, STI))
2910 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2911 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
2921 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2924 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2929 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
2937 Is32BitImm, false, IDLoc, Out, STI))
2945 bool Is32BitAddress, SMLoc IDLoc,
2950 Warning(IDLoc, "la used to load 64-bit address");
2957 Error(IDLoc, "instruction requires a 64-bit architecture");
2963 Is32BitAddress, IDLoc, Out, STI);
2971 IDLoc, Out, STI);
2976 bool Is32BitSym, SMLoc IDLoc,
2982 warnIfNoMacro(IDLoc);
2987 Error(IDLoc, "expected relocatable expression");
2991 Error(IDLoc, "expected relocatable expression with only one symbol");
3020 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc,
3023 IDLoc, STI);
3025 MCOperand::createExpr(CallLoExpr), IDLoc, STI);
3030 MCOperand::createExpr(CallExpr), IDLoc, STI);
3041 unsigned ATReg = getATReg(IDLoc);
3065 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc,
3068 IDLoc, STI);
3070 MCOperand::createExpr(CallLoExpr), IDLoc, STI);
3076 IDLoc, STI);
3080 IDLoc, STI);
3105 Error(IDLoc, "macro instruction uses large offset, which is not "
3137 MCOperand::createExpr(GotExpr), IDLoc, STI);
3141 MCOperand::createExpr(LoExpr), IDLoc, STI);
3145 IDLoc, STI);
3174 unsigned ATReg = getATReg(IDLoc);
3184 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3187 MCOperand::createExpr(HigherExpr), IDLoc, STI);
3188 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3190 IDLoc, STI);
3191 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3193 IDLoc, STI);
3194 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
3197 } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) {
3198 unsigned ATReg = getATReg(IDLoc);
3211 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3213 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3215 MCOperand::createExpr(HigherExpr), IDLoc, STI);
3217 IDLoc, STI);
3218 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
3219 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
3221 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3225 (canUseATReg() && DstReg == getATReg(IDLoc))) {
3234 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3237 MCOperand::createExpr(HigherExpr), IDLoc, STI);
3238 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3240 MCOperand::createExpr(HiExpr), IDLoc, STI);
3241 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3243 MCOperand::createExpr(LoExpr), IDLoc, STI);
3245 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3253 reportParseError(IDLoc,
3273 unsigned ATReg = getATReg(IDLoc);
3279 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3281 IDLoc, STI);
3284 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3357 bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
3359 unsigned ATReg = getATReg(IDLoc);
3371 IDLoc, STI);
3374 IDLoc, STI);
3389 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3400 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3403 MCOperand::createExpr(HigherExpr), IDLoc, STI);
3404 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3406 IDLoc, STI);
3407 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3431 bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc,
3443 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,
3447 bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
3464 TmpReg = getATReg(IDLoc);
3471 true, false, IDLoc, Out, STI))
3473 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
3490 getStreamer().emitLabel(Sym, IDLoc);
3494 if (emitPartialAddress(TOut, IDLoc, Sym))
3497 IDLoc, STI);
3501 bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
3517 IDLoc, Out, STI))
3521 IDLoc, Out, STI))
3525 IDLoc, Out, STI))
3542 getStreamer().emitLabel(Sym, IDLoc);
3547 unsigned TmpReg = getATReg(IDLoc);
3551 if (emitPartialAddress(TOut, IDLoc, Sym))
3555 MCOperand::createExpr(LoExpr), IDLoc, STI);
3558 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
3560 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
3561 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
3567 SMLoc IDLoc, MCStreamer &Out,
3581 TmpReg = getATReg(IDLoc);
3590 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
3593 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
3599 IDLoc, Out, STI))
3603 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3604 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
3606 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
3607 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3625 getStreamer().emitLabel(Sym, IDLoc);
3630 if (emitPartialAddress(TOut, IDLoc, Sym))
3634 MCOperand::createExpr(LoExpr), IDLoc, STI);
3639 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
3663 return Error(IDLoc, "branch target out of range");
3665 return Error(IDLoc, "branch to misaligned address");
3679 TOut.emitEmptyDelaySlot(true, IDLoc, STI);
3684 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3724 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
3725 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3727 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3730 warnIfNoMacro(IDLoc);
3732 unsigned ATReg = getATReg(IDLoc);
3737 IDLoc, Out, STI))
3742 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
3743 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3745 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
3750 void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3778 TmpReg = getATReg(IDLoc);
3785 TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI);
3787 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI);
3804 IDLoc, Out, STI))
3810 TmpReg, BaseReg, IDLoc, STI);
3825 Error(IDLoc, "expected relocatable expression");
3829 Error(IDLoc, "expected relocatable expression with only one symbol");
3834 !ABI.ArePtrs64bit(), IDLoc, Out, STI);
3854 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI);
3855 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI);
3856 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
3857 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI);
3858 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
3860 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
3864 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
3866 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
3877 void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3905 TmpReg = getATReg(IDLoc);
3912 TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI);
3915 IDLoc, STI);
3920 IDLoc, Out, STI);
3927 !ABI.ArePtrs64bit(), IDLoc, Out, STI);
3935 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
3964 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
3981 warnIfNoMacro(IDLoc);
3984 TrgReg = getATReg(IDLoc);
4042 false, IDLoc, Out, STI))
4107 IDLoc, STI);
4112 IDLoc, STI);
4113 Warning(IDLoc, "branch is always taken");
4118 IDLoc, STI);
4119 Warning(IDLoc, "branch is always taken");
4124 IDLoc, STI);
4129 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
4136 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
4137 Warning(IDLoc, "branch is always taken");
4161 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
4162 Warning(IDLoc, "branch is always taken");
4180 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
4188 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
4194 unsigned ATRegNum = getATReg(IDLoc);
4199 warnIfNoMacro(IDLoc);
4218 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI);
4222 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
4235 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4240 warnIfNoMacro(IDLoc);
4289 unsigned ATReg = getATReg(IDLoc);
4295 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4297 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4302 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
4305 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
4308 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
4314 TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);
4315 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4327 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4330 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4337 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
4347 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
4352 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
4355 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
4358 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4364 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4368 unsigned ATReg = getATReg(IDLoc);
4375 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
4383 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
4386 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
4387 TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI);
4389 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
4393 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
4396 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
4397 TOut.emitNop(IDLoc, STI);
4398 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
4402 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4407 SMLoc IDLoc, MCStreamer &Out,
4420 unsigned ATReg = getATReg(IDLoc);
4423 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4424 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4425 TOut.emitNop(IDLoc, STI);
4426 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
4427 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
4428 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
4429 TOut.emitNop(IDLoc, STI);
4432 FirstReg, SecondReg, IDLoc, STI);
4433 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
4434 TOut.emitNop(IDLoc, STI);
4440 FirstReg, SecondReg, IDLoc, STI);
4445 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
4448 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4465 warnIfNoMacro(IDLoc);
4466 unsigned ATReg = getATReg(IDLoc);
4473 IDLoc, Out, STI))
4489 FirstOffset, IDLoc, STI);
4490 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI);
4491 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
4492 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4497 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4500 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4515 warnIfNoMacro(IDLoc);
4516 unsigned ATReg = getATReg(IDLoc);
4523 IDLoc, Out, STI))
4533 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI);
4534 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI);
4535 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI);
4536 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI);
4537 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI);
4538 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4540 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI);
4541 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI);
4542 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI);
4548 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4551 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4577 warnIfNoMacro(IDLoc);
4578 TmpReg = getATReg(IDLoc);
4585 IDLoc, Out, STI))
4594 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI);
4595 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);
4598 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4603 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4617 warnIfNoMacro(IDLoc);
4631 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
4632 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4637 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4651 warnIfNoMacro(IDLoc);
4671 TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
4672 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4683 false, IDLoc, Out, STI))
4686 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
4687 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4693 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4708 warnIfNoMacro(IDLoc);
4731 false, IDLoc, Out, STI))
4735 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
4740 bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4754 warnIfNoMacro(IDLoc);
4768 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI);
4769 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4774 bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4788 warnIfNoMacro(IDLoc);
4813 false, IDLoc, Out, STI))
4816 TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
4817 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4822 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
4921 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
4923 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
4929 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4991 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
5054 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5116 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
5211 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5217 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
5219 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
5221 TOut.emitEmptyDelaySlot(false, IDLoc, STI);
5222 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
5227 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5235 ATReg = getATReg(IDLoc);
5239 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out,
5243 SrcReg, ATReg, IDLoc, STI);
5245 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5250 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5263 SrcReg, TmpReg, IDLoc, STI);
5265 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5268 DstReg, DstReg, 0x1F, IDLoc, STI);
5270 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
5273 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI);
5280 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);
5282 TOut.emitNop(IDLoc, STI);
5283 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
5287 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5292 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5300 ATReg = getATReg(IDLoc);
5305 SrcReg, TmpReg, IDLoc, STI);
5307 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
5308 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5310 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
5317 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
5319 TOut.emitNop(IDLoc, STI);
5320 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
5328 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5335 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
5336 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5346 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
5353 warnIfNoMacro(IDLoc);
5363 warnIfRegIndexIsAT(FirstReg, IDLoc);
5378 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5379 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5381 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5382 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5394 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc,
5400 warnIfNoMacro(IDLoc);
5410 warnIfRegIndexIsAT(FirstReg, IDLoc);
5425 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5426 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5431 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5444 warnIfNoMacro(IDLoc);
5447 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
5448 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5453 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
5457 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5470 warnIfNoMacro(IDLoc);
5473 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI);
5478 Warning(IDLoc, "comparison is always false");
5480 DstReg, SrcReg, SrcReg, IDLoc, STI);
5493 unsigned ATReg = getATReg(IDLoc);
5497 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
5501 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
5502 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5506 TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI);
5507 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5511 bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5525 warnIfNoMacro(IDLoc);
5528 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
5529 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
5534 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);
5538 bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5551 warnIfNoMacro(IDLoc);
5554 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI);
5559 Warning(IDLoc, "comparison is always true");
5560 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out,
5575 TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI);
5576 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
5580 unsigned ATReg = getATReg(IDLoc);
5585 false, IDLoc, Out, STI))
5588 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
5589 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
5729 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5794 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
5799 bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5805 warnIfNoMacro(IDLoc);
5816 TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI);
5821 unsigned ATReg = getATReg(IDLoc);
5825 if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI))
5828 TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI);
5998 bool MipsAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
6009 if (processInstruction(Inst, IDLoc, Out, STI))
6013 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
6016 Error(IDLoc, "operand must match destination register");
6019 SMLoc ErrorLoc = IDLoc;
6022 return Error(IDLoc, "too few operands for instruction");
6026 ErrorLoc = IDLoc;
6032 return Error(IDLoc,
6035 return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs");
6037 return Error(IDLoc, "invalid instruction");
6039 return Error(IDLoc, "source and destination must be different");
6041 return Error(IDLoc, "registers must be different");
6043 return Error(IDLoc, "invalid operand ($zero) for instruction");
6045 return Error(IDLoc, "source and destination must match");
6047 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6050 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'");
6052 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6055 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6058 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6061 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6064 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6067 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6070 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6073 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6076 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6079 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6082 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6087 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6090 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6093 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6096 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6099 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6102 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6105 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6108 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6111 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6114 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6117 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6120 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6123 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6128 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6132 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6135 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6138 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6141 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6145 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6148 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6151 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6154 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6157 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6160 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6163 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6166 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6169 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6172 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
6175 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),