Lines Matching defs:DstRegOp

2933   const MCOperand &DstRegOp = Inst.getOperand(0);
2934   assert(DstRegOp.isReg() && "expected register operand kind");
2936   if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
3687   const MCOperand &DstRegOp = Inst.getOperand(0);
3688   assert(DstRegOp.isReg() && "expected register operand kind");
3723       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
3727       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3741       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,
3745       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
3756   const MCOperand &DstRegOp = Inst.getOperand(StartOp);
3757   assert(DstRegOp.isReg() && "expected register operand kind");
3764   unsigned DstReg = DstRegOp.getReg();
3883   const MCOperand &DstRegOp = Inst.getOperand(StartOp);
3884   assert(DstRegOp.isReg() && "expected register operand kind");
3891   unsigned DstReg = DstRegOp.getReg();
4451   const MCOperand &DstRegOp = Inst.getOperand(0);
4452   assert(DstRegOp.isReg() && "expected register operand kind");
4459   unsigned DstReg = DstRegOp.getReg();
4503   const MCOperand &DstRegOp = Inst.getOperand(0);
4504   assert(DstRegOp.isReg() && "expected register operand kind");
4511   unsigned DstReg = DstRegOp.getReg();
4554   const MCOperand &DstRegOp = Inst.getOperand(0);
4555   assert(DstRegOp.isReg() && "expected register operand kind");
4562   unsigned DstReg = DstRegOp.getReg();