Lines Matching defs:SrcReg

43                                      MCRegister SrcReg, bool KillSrc,
46   if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
48         .addReg(SrcReg, getKillRegState(KillSrc))
54   if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) {
56         .addReg(SrcReg, getKillRegState(KillSrc))
62   if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) {
64         .addReg(SrcReg, getKillRegState(KillSrc))
71       LoongArch::GPRRegClass.contains(SrcReg)) {
73         .addReg(SrcReg, getKillRegState(KillSrc));
78       LoongArch::CFRRegClass.contains(SrcReg)) {
80         .addReg(SrcReg, getKillRegState(KillSrc));
84   if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) {
86         .addReg(SrcReg, getKillRegState(KillSrc));
92   if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
94   } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
97              LoongArch::FPR32RegClass.contains(SrcReg)) {
101              LoongArch::FPR64RegClass.contains(SrcReg)) {
110       .addReg(SrcReg, getKillRegState(KillSrc));
114     MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
144       .addReg(SrcReg, getKillRegState(IsKill))
192   Register SrcReg = LoongArch::R0;
212           .addReg(SrcReg, RegState::Kill)
218           .addReg(SrcReg, RegState::Kill)
219           .addReg(SrcReg, RegState::Kill)
229     SrcReg = DstReg;