Lines Matching defs:HexagonSubtarget

1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
13 #include "HexagonSubtarget.h"
75 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
89 HexagonSubtarget &
90 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
171 bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const {
182 bool HexagonSubtarget::isHVXVectorType(EVT VecTy, bool IncludeBool) const {
210 bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const {
245 void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {
258 void HexagonSubtarget::HVXMemLatencyMutation::apply(ScheduleDAGInstrs *DAG) {
297 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
309 void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
318   auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
377 void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
427 bool HexagonSubtarget::useAA() const {
435 void HexagonSubtarget::adjustSchedDependency(
512 void HexagonSubtarget::getPostRAMutations(
519 void HexagonSubtarget::getSMSMutations(
526 void HexagonSubtarget::anchor() {}
528 bool HexagonSubtarget::enableMachineScheduler() const {
534 bool HexagonSubtarget::usePredicatedCalls() const {
538 int HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
553 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
602 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
631 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
716 unsigned HexagonSubtarget::getL1CacheLineSize() const {
720 unsigned HexagonSubtarget::getL1PrefetchDistance() const {
724 bool HexagonSubtarget::enableSubRegLiveness() const { return true; }
726 Intrinsic::ID HexagonSubtarget::getIntrinsicId(unsigned Opc) const {