HexagonSplitDouble.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp

Lines Matching defs:Op1
343       const MachineOperand &Op1 = MI->getOperand(1);
345       int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0;
698   MachineOperand &Op1 = MI->getOperand(1);
699   assert(Op0.isReg() && Op1.isImm());
700   uint64_t V = Op1.getImm();
725   MachineOperand &Op1 = MI->getOperand(1);
735   if (!Op1.isReg()) {
737       .add(Op1);
740       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
755   MachineOperand &Op1 = MI->getOperand(1);
756   assert(Op0.isReg() && Op1.isReg());
763   unsigned RS = getRegState(Op1);
766     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
768     .addReg(Op1.getReg(), RS, Op1.getSubReg())
777   MachineOperand &Op1 = MI->getOperand(1);
779   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
797   unsigned RS = getRegState(Op1);
806       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
808       .addReg(Op1.getReg(), RS, HiSR);
831         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
834         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
837         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
843         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
849         .addReg(Op1.getReg(), RS, HiSR)
854         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
859         .addReg(Op1.getReg(), RS, HiSR)
865       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
871         .addReg(Op1.getReg(), RS, HiSR)
877         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
880         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
883         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
888         .addReg(Op1.getReg(), RS, HiSR)
901   MachineOperand &Op1 = MI->getOperand(1);
904   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
917   unsigned RS1 = getRegState(Op1);
924   // Op0 = S2_asl_i_p_or Op1, Op2, Op3
925   // means:  Op0 = or (Op1, asl(Op2, Op3))
941       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
944       .addReg(Op1.getReg(), RS1, HiSR)
948       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
958       .addReg(Op1.getReg(), RS1, HiSR)
970       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
972       .addReg(Op1.getReg(), RS1, HiSR)
981       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
983       .addReg(Op1.getReg(), RS1, HiSR)