Lines Matching defs:LoSR

800   unsigned LoSR = isub_lo;
806       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
831         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
834         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
837         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
843         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
865       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
877         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
883         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
921   unsigned LoSR = isub_lo;
941       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
942       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
948       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
949       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
953       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
970       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
973       .addReg(Op2.getReg(), RS2, LoSR);
981       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
984       .addReg(Op2.getReg(), RS2, LoSR)