Lines Matching defs:HexagonSplitDoubleRegs
63 class HexagonSplitDoubleRegs : public MachineFunctionPass {
67 HexagonSplitDoubleRegs() : MachineFunctionPass(ID) {}
127 char HexagonSplitDoubleRegs::ID;
128 int HexagonSplitDoubleRegs::Counter = 0;
129 const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC =
132 INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
136 LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
145 bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
154 bool HexagonSplitDoubleRegs::isVolatileInstr(const MachineInstr *MI) const {
161 bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
220 void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
313 int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
400 int32_t HexagonSplitDoubleRegs::profit(Register Reg) const {
419 bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
474 void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
570 void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
588 void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
622 void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
695 void HexagonSplitDoubleRegs::splitImmediate(MachineInstr *MI,
722 void HexagonSplitDoubleRegs::splitCombine(MachineInstr *MI,
752 void HexagonSplitDoubleRegs::splitExt(MachineInstr *MI,
772 void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
896 void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
989 bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI,
1072 void HexagonSplitDoubleRegs::replaceSubregUses(MachineInstr *MI,
1094 void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
1121 bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
1183 bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
1232 return new HexagonSplitDoubleRegs();