Lines Matching defs:HexagonInstrInfo

1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
13 #include "HexagonInstrInfo.h"
118 void HexagonInstrInfo::anchor() {}
120 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
154 bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
185 bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {
197 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
288 Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
336 Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
386 bool HexagonInstrInfo::hasLoadFromStackSlot(
404 bool HexagonInstrInfo::hasStoreToStackSlot(
434 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
604 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
627 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
730   const HexagonInstrInfo *TII;
808 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
822 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
828 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
835 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
859 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
962 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1011 void HexagonInstrInfo::loadRegFromStackSlot(
1055 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1549 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1637 bool HexagonInstrInfo::reverseBranchCondition(
1652 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1658 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1670 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1675 bool HexagonInstrInfo::PredicateInstruction(
1727 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1733 bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI,
1760 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1796 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1844 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1872 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1883 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1973 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1979 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1989 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
2047 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
2070 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2076 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2095 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2104 Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2121 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2125 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2130 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2134 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2143 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2149 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2198 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2213 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2244 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2255 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2263 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2270 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2275 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2289 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2311 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2324 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2331 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2340 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2351 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2365 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2383 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2425 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2431 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2443 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2475 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2480 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2485 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2489 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2493 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2497 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2502 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2508 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2515 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2521 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2527 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2533 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2541 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2546 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2551 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2558 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2565 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2643 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2648 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2658 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2669 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2674 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2679 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2684 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2690 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2708 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2714 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2751 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2961 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2965 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2973 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2987 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
3066 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
3075 bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
3088 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
3113 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
3118 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
3127 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
3162 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3167 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3179 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3186 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3194 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3212 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3232 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3267 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3278 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3284 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3294 HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
3326 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3363 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3421 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3428 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3516 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3543 int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,
3600 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3612 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3632 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3733 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3774 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3860 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3875 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3926 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
4306 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4310 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4330 std::optional<unsigned> HexagonInstrInfo::getOperandLatency(
4374 bool HexagonInstrInfo::getInvertedPredSense(
4383 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4394 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4408 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4436 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {
4448 bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {
4454 void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
4472 void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF,
4482 void HexagonInstrInfo::translateInstrsForDup(
4491 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4514 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4528 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4552 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4572 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4576 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4584 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4618 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4623 InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4631 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4635 unsigned HexagonInstrInfo::nonDbgBundleSize(
4645 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4658 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4679 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4701 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4708 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4719 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4724 void HexagonInstrInfo::
4734 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4741 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4745 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4749 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4753 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4757 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
4761 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
4765 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
4769 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
4773 MCInst HexagonInstrInfo::getNop() const {