Lines Matching defs:VecV

1001     // down to match the representation (bytes per type element) that VecV
1004     // vector. This subvector will then be inserted into the Q2V of VecV.
1151 HexagonTargetLowering::extractHvxElementReg(SDValue VecV, SDValue IdxV,
1153   MVT ElemTy = ty(VecV).getVectorElementType();
1161                                {VecV, ByteIdx});
1175 HexagonTargetLowering::extractHvxElementPred(SDValue VecV, SDValue IdxV,
1182   SDValue ByteVec = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, VecV);
1184   unsigned Scale = HwLen / ty(VecV).getVectorNumElements();
1194 HexagonTargetLowering::insertHvxElementReg(SDValue VecV, SDValue IdxV,
1196   MVT ElemTy = ty(VecV).getVectorElementType();
1202   auto InsertWord = [&DAG,&dl,this] (SDValue VecV, SDValue ValV,
1204     MVT VecTy = ty(VecV);
1209     SDValue RotV = DAG.getNode(HexagonISD::VROR, dl, VecTy, {VecV, MaskV});
1219     return InsertWord(VecV, ValV, ByteIdx);
1225   SDValue Ext = extractHvxElementReg(opCastElem(VecV, MVT::i32, DAG), WordIdx,
1236   return InsertWord(VecV, Ins, ByteIdx);
1240 HexagonTargetLowering::insertHvxElementPred(SDValue VecV, SDValue IdxV,
1244   SDValue ByteVec = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, VecV);
1246   unsigned Scale = HwLen / ty(VecV).getVectorNumElements();
1252   return DAG.getNode(HexagonISD::V2Q, dl, ty(VecV), InsV);
1256 HexagonTargetLowering::extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV,
1258   MVT VecTy = ty(VecV);
1271     VecV = OrigOp;
1273       return VecV;
1281   SDValue WordVec = DAG.getBitcast(WordTy, VecV);
1296 HexagonTargetLowering::extractHvxSubvectorPred(SDValue VecV, SDValue IdxV,
1298   MVT VecTy = ty(VecV);
1301   SDValue ByteVec = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, VecV);
1360 HexagonTargetLowering::insertHvxSubvectorReg(SDValue VecV, SDValue SubV,
1362   MVT VecTy = ty(VecV);
1370   // The two single vectors that VecV consists of, if it's a pair.
1372   SDValue SingleV = VecV;
1376     V0 = LoHalf(VecV, DAG);
1377     V1 = HiHalf(VecV, DAG);
1387         return DAG.getTargetInsertSubreg(SubIdx, dl, VecTy, VecV, SubV);
1447 HexagonTargetLowering::insertHvxSubvectorPred(SDValue VecV, SDValue SubV,
1449   MVT VecTy = ty(VecV);
1452   // VecV is an HVX vector predicate. SubV may be either an HVX vector
1464   SDValue ByteVec = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, VecV);
1475   // ByteVec is the target vector VecV rotated in such a way that the
1493 HexagonTargetLowering::extendHvxVectorPred(SDValue VecV, const SDLoc &dl,
1500     return DAG.getNode(HexagonISD::Q2V, dl, ResTy, VecV);
1502   assert(ty(VecV).getVectorNumElements() == ResTy.getVectorNumElements());
1506   return DAG.getSelect(dl, ResTy, VecV, True, False);
1567 HexagonTargetLowering::resizeToWidth(SDValue VecV, MVT ResTy, bool Signed,
1570   MVT InpTy = ty(VecV);
1572     return VecV;
1579                ? DAG.getNode(ISD::FP_EXTEND, dl, ResTy, VecV)
1580                : DAG.getNode(ISD::FP_ROUND, dl, ResTy, VecV,
1588     return DAG.getNode(ExtOpc, dl, ResTy, VecV);
1591     return DAG.getNode(NarOpc, dl, ResTy, VecV, DAG.getValueType(ResTy));
1766   SDValue VecV = Op.getOperand(0);
1767   MVT ElemTy = ty(VecV).getVectorElementType();
1771     return extractHvxElementPred(VecV, IdxV, dl, ty(Op), DAG);
1773   return extractHvxElementReg(VecV, IdxV, dl, ty(Op), DAG);
1781   SDValue VecV = Op.getOperand(0);
1784   MVT ElemTy = ty(VecV).getVectorElementType();
1786     return insertHvxElementPred(VecV, IdxV, ValV, dl, DAG);
1791         DAG.getBitcast(tyVector(VecTy, MVT::i16), VecV),
1796   return insertHvxElementReg(VecV, IdxV, ValV, dl, DAG);
1822   SDValue VecV = Op.getOperand(0);
1827   MVT VecTy = ty(VecV);
1830     return insertHvxSubvectorPred(VecV, ValV, IdxV, dl, DAG);
1832   return insertHvxSubvectorReg(VecV, ValV, IdxV, dl, DAG);