Lines Matching defs:SubV

1000     // Move the vector predicate SubV to a vector register, and scale it
1211     SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32,
1213     SDValue TorV = DAG.getNode(HexagonISD::VROR, dl, VecTy, {InsV, SubV});
1360 HexagonTargetLowering::insertHvxSubvectorReg(SDValue VecV, SDValue SubV,
1363   MVT SubTy = ty(SubV);
1387         return DAG.getTargetInsertSubreg(SubIdx, dl, VecTy, VecV, SubV);
1390       // SubV as the high and as the low subregister, and select the right
1392       SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1});
1393       SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV});
1419     SDValue V = DAG.getBitcast(MVT::i32, SubV);
1422     SDValue V = DAG.getBitcast(MVT::i64, SubV);
1447 HexagonTargetLowering::insertHvxSubvectorPred(SDValue VecV, SDValue SubV,
1450   MVT SubTy = ty(SubV);
1452   // VecV is an HVX vector predicate. SubV may be either an HVX vector
1465   SDValue ByteSub = createHvxPrefixPred(SubV, dl, BitBytes, false, DAG);