HexagonHardwareLoops.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

Lines Matching defs:TB
458   MachineBasicBlock *TB = nullptr, *FB = nullptr;
459   bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
620   MachineBasicBlock *TB = nullptr, *FB = nullptr;
621   bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
626   // TB must be non-null.  If FB is also non-null, one of them must be
627   // the header.  Otherwise, branch to TB could be exiting the loop, and
629   assert (TB && "Exit block without a branch?");
630   if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
636     if (TB == Latch)
637       TB = (LTB == Header) ? LTB : LFB;
641   assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");
642   if (!TB || (FB && TB != Header && FB != Header))
647   // If TB is not the header, it means that the "not-taken" path must lead
649   bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
1224     MachineBasicBlock *TB = nullptr, *FB = nullptr;
1227     if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false))
1230     if (L->contains(TB))
1231       LoopStart = TB;
1641   MachineBasicBlock *TB = nullptr, *FB = nullptr;
1644   bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
1648   if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
1657     if (TB == Latch)
1658       TB = (LTB == Header) ? LTB : LFB;
1662   if (TB != Header) {
1668     // In this case, the LoopBody -> TB should not be a back edge otherwise
1671     // Jmp_c OuterLoopHeader <-- TB
1673     if (MDT->dominates(TB, FB))
1859   MachineBasicBlock *TB = nullptr, *FB = nullptr;
1861   if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false))
1865     bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
1944   TB = FB = nullptr;
1949       bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false);
1952       if (TB != Header && (Tmp2.empty() || FB != Header))
1960   TB = FB = nullptr;
1961   bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false);
1964   if (!TB && !FB)