Lines Matching defs:SRegs

1562   BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1564   // Generate a set of unique, callee-saved registers (SRegs), where each
1566   // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1569   // sub-registers to SRegs.
1575       SRegs[SR] = true;
1578   LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1582   // sub- and super-registers from SRegs.
1607       SRegs[SR] = false;
1611   LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1614   // (3) Collect all registers that have at least one sub-register in SRegs,
1619   for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1636   // (4) Include all super-registers found in (3) into SRegs.
1637   SRegs |= TmpSup;
1638   LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1641   // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1642   // remove R from SRegs.
1643   for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1646       if (!SRegs[SR])
1648       SRegs[R] = false;
1652   LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1665     if (!SRegs[S->Reg])
1671     SRegs[S->Reg] = false;
1677   for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1687     SRegs[R] = false;
1706   for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {