Lines Matching defs:Register

18 #include "llvm/CodeGen/Register.h"
232     struct Register {
233       Register() = default;
234       Register(llvm::Register R, unsigned S) : Reg(R), Sub(S) {}
235       Register(const MachineOperand &Op)
237       Register &operator=(const MachineOperand &Op) {
242           Reg = llvm::Register::index2StackSlot(Op.getIndex());
256           int FI = llvm::Register::stackSlot2Index(Reg);
261       bool operator==(Register R) const { return Reg == R.Reg && Sub == R.Sub; }
262       bool operator!=(Register R) const { return !operator==(R); }
263       bool operator<(Register R) const {
267       llvm::Register Reg;
293       Register Rs;
298       ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
325       Register Rd;
394     OffsetRange getOffsetRange(Register R, const MachineInstr &MI) const;
396     OffsetRange getOffsetRange(Register Rd) const;
405     Register insertInitializer(Loc DefL, const ExtenderInit &ExtI);
406     bool replaceInstrExact(const ExtDesc &ED, Register ExtR);
408                           Register ExtR, int32_t &Diff);
409     bool replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI);
445     PrintRegister(HCE::Register R, const HexagonRegisterInfo &I)
447     HCE::Register Rs;
1049 OffsetRange HCE::getOffsetRange(Register Rb, const MachineInstr &MI) const {
1058     if (Rb != Register(Op1) || !Op2.isImm())
1073       Rb != Register(MI.getOperand(BaseP)) ||
1129 OffsetRange HCE::getOffsetRange(Register Rd) const {
1135     if (Rd != Register(Op))
1508   Register Rs = ExtI.second.Rs;  // Only one reg allowed now.
1532 HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) {
1533   llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1581         llvm::Register TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1588                     .add(MachineOperand(Register(TmpR, 0)));
1591                     .add(MachineOperand(Register(TmpR, 0)))
1606 bool HCE::replaceInstrExact(const ExtDesc &ED, Register ExtR) {
1724       Register ExtR, int32_t &Diff) {
1805     Register Rs = MI.getOperand(IsSub ? 3 : 2);
1848 bool HCE::replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI) {
1928       Register DefR = insertInitializer(Q.first, P.first);