Lines Matching +defs:lo +defs:size

68     // If pointer size is not set through target data, it will default to
163     for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
172   size_t size() const { return Vector.size(); }
176     assert(n < Vector.size());
252   if (Reg.size() == 0)
273   auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
344       uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
353       uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
392       RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
397       RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
402       RegisterCell RC = eADD(rc(1), lo(M, W0));
407       RegisterCell RC = eADD(rc(1), lo(M, W0));
412       RegisterCell RC = eADD(rc(1), lo(M, W0));
477       return rr0(lo(M, W0), Outputs);
481       RegisterCell RC = eADD(rc(1), lo(M, W0));
486       RegisterCell RC = eSUB(rc(1), lo(M, W0));
491       RegisterCell RC = eADD(rc(1), lo(M, W0));
496       RegisterCell RC = eSUB(rc(1), lo(M, W0));
501       return rr0(lo(M, 32), Outputs);
505       return rr0(lo(M, 32), Outputs);
509       return rr0(lo(M, 32), Outputs);
719       // If the width extends beyond the register size, pad the register
793       uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
968           uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);