Lines Matching defs:RR
239 static bool getSubregMask(const BitTracker::RegisterRef &RR,
255 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
435 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
437 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
438 if (RR.Sub == 0) {
450 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
926 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
927 if (!RR.Reg.isVirtual())
929 auto *RC = MRI.getRegClass(RR.Reg);
930 if (RR.Sub == 0)
943 VerifySR(RC, RR.Sub);
946 VerifySR(RC, RR.Sub);
1289 BitTracker::RegisterRef RR = MI.getOperand(OpN);
1290 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
2384 BitTracker::RegisterRef RR(V.RefI.Reg, 0);
2387 RR.Sub = Hexagon::isub_lo;
2390 RR.Sub = Hexagon::isub_hi;
2398 .addReg(RR.Reg, 0, RR.Sub)