Lines Matching defs:FrameReg

424                                           Register FrameReg, int &Offset,
441     emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
451     unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
464       Register DestReg = FrameReg;
466       // In case FrameReg is a high register, move it to a low reg to ensure it
468       if (ARM::hGPRRegClass.contains(FrameReg) && FrameReg != ARM::SP) {
471             .addReg(FrameReg)
481       if (NewOpc != Opcode && FrameReg != ARM::SP)
495     if (FrameReg == ARM::SP && Offset - (Mask * Scale) <= 1020) {
555   Register FrameReg;
558   int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
565   if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
577     MI.getOperand(FIOperandNum).  ChangeToRegister(FrameReg, false /*isDef*/);
585   if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
605       if (FrameReg == ARM::SP || STI.genExecuteOnly())
606         emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
610         if (!ARM::hGPRRegClass.contains(FrameReg)) {
613           // If FrameReg is a high register, add the reg values in a separate
617               .addReg(FrameReg)
622       emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
629       assert(!ARM::hGPRRegClass.contains(FrameReg) &&
633       MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
641         if (FrameReg == ARM::SP || STI.genExecuteOnly())
642           emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
646           if (!ARM::hGPRRegClass.contains(FrameReg)) {
649             // If FrameReg is a high register, add the reg values in a separate
653                 .addReg(FrameReg)
658         emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
663         assert(!ARM::hGPRRegClass.contains(FrameReg) &&
667         MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,