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1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
33 #define DEBUG_TYPE "asm-printer"
38 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
40 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
50 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
54 O << ", ";
57 O << getShiftOpcStr(ShOpc);
60 O << " ";
61 printer.markup(O, llvm::MCInstPrinter::Markup::Immediate)
71 if (Opt == "reg-names-std") {
75 if (Opt == "reg-names-raw") {
88 raw_ostream &O) {
89 unsigned Opcode = MI->getOpcode();
93 const MCOperand &Reg = MI->getOperand(0);
94 O << '\t' << "vlldm" << '\t';
95 printRegName(O, Reg.getReg());
96 O << ", "
97 << "{d0 - d15}";
101 const MCOperand &Reg = MI->getOperand(0);
102 O << '\t' << "vlldm" << '\t';
103 printRegName(O, Reg.getReg());
104 O << ", "
105 << "{d0 - d31}";
109 const MCOperand &Reg = MI->getOperand(0);
110 O << '\t' << "vlstm" << '\t';
111 printRegName(O, Reg.getReg());
112 O << ", "
113 << "{d0 - d15}";
117 const MCOperand &Reg = MI->getOperand(0);
118 O << '\t' << "vlstm" << '\t';
119 printRegName(O, Reg.getReg());
120 O << ", "
121 << "{d0 - d31}";
127 const MCOperand &Dst = MI->getOperand(0);
128 const MCOperand &MO1 = MI->getOperand(1);
129 const MCOperand &MO2 = MI->getOperand(2);
130 const MCOperand &MO3 = MI->getOperand(3);
132 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
133 printSBitModifierOperand(MI, 6, STI, O);
134 printPredicateOperand(MI, 4, STI, O);
136 O << '\t';
137 printRegName(O, Dst.getReg());
138 O << ", ";
139 printRegName(O, MO1.getReg());
141 O << ", ";
142 printRegName(O, MO2.getReg());
144 printAnnotation(O, Annot);
150 const MCOperand &Dst = MI->getOperand(0);
151 const MCOperand &MO1 = MI->getOperand(1);
152 const MCOperand &MO2 = MI->getOperand(2);
154 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
155 printSBitModifierOperand(MI, 5, STI, O);
156 printPredicateOperand(MI, 3, STI, O);
158 O << '\t';
159 printRegName(O, Dst.getReg());
160 O << ", ";
161 printRegName(O, MO1.getReg());
164 printAnnotation(O, Annot);
168 O << ", ";
169 markup(O, Markup::Immediate)
171 printAnnotation(O, Annot);
178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
180 O << '\t' << "push";
181 printPredicateOperand(MI, 2, STI, O);
183 O << ".w";
184 O << '\t';
185 printRegisterList(MI, 4, STI, O);
186 printAnnotation(O, Annot);
192 if (MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(3).getImm() == -4) {
194 O << '\t' << "push";
195 printPredicateOperand(MI, 4, STI, O);
196 O << "\t{";
197 printRegName(O, MI->getOperand(1).getReg());
198 O << "}";
199 printAnnotation(O, Annot);
207 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
209 O << '\t' << "pop";
210 printPredicateOperand(MI, 2, STI, O);
212 O << ".w";
213 O << '\t';
214 printRegisterList(MI, 4, STI, O);
215 printAnnotation(O, Annot);
221 if (MI->getOperand(2).getReg() == ARM::SP &&
222 MI->getOperand(4).getImm() == 4) {
223 O << '\t' << "pop";
224 printPredicateOperand(MI, 5, STI, O);
225 O << "\t{";
226 printRegName(O, MI->getOperand(0).getReg());
227 O << "}";
228 printAnnotation(O, Annot);
236 if (MI->getOperand(0).getReg() == ARM::SP) {
237 O << '\t' << "vpush";
238 printPredicateOperand(MI, 2, STI, O);
239 O << '\t';
240 printRegisterList(MI, 4, STI, O);
241 printAnnotation(O, Annot);
249 if (MI->getOperand(0).getReg() == ARM::SP) {
250 O << '\t' << "vpop";
251 printPredicateOperand(MI, 2, STI, O);
252 O << '\t';
253 printRegisterList(MI, 4, STI, O);
254 printAnnotation(O, Annot);
261 MCRegister BaseReg = MI->getOperand(0).getReg();
262 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
263 if (MI->getOperand(i).getReg() == BaseReg)
267 O << "\tldm";
269 printPredicateOperand(MI, 1, STI, O);
270 O << '\t';
271 printRegName(O, BaseReg);
273 O << "!";
274 O << ", ";
275 printRegisterList(MI, 3, STI, O);
276 printAnnotation(O, Annot);
292 MCRegister Reg = MI->getOperand(isStore ? 1 : 0).getReg();
299 NewMI.addOperand(MI->getOperand(0));
305 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
306 NewMI.addOperand(MI->getOperand(i));
307 printInstruction(&NewMI, Address, STI, O);
314 O << "\ttsb\tcsync";
317 switch (MI->getOperand(0).getImm()) {
319 if (!printAliasInstr(MI, Address, STI, O))
320 printInstruction(MI, Address, STI, O);
323 O << "\tssbb";
326 O << "\tpssbb";
329 printAnnotation(O, Annot);
333 if (!printAliasInstr(MI, Address, STI, O))
334 printInstruction(MI, Address, STI, O);
336 printAnnotation(O, Annot);
340 const MCSubtargetInfo &STI, raw_ostream &O) {
341 const MCOperand &Op = MI->getOperand(OpNo);
344 printRegName(O, Reg);
346 markup(O, Markup::Immediate) << '#' << formatImm(Op.getImm());
350 switch (Expr->getKind()) {
352 O << '#';
353 Expr->print(O, &MAI);
361 if (!Constant->evaluateAsAbsolute(TargetAddress)) {
362 O << '#';
363 Expr->print(O, &MAI);
365 O << "0x";
366 O.write_hex(static_cast<uint32_t>(TargetAddress));
373 Expr->print(O, &MAI);
381 raw_ostream &O) {
382 const MCOperand &Op = MI->getOperand(OpNum);
384 return printOperand(MI, OpNum, STI, O);
385 uint64_t Target = ARM_MC::evaluateBranchTarget(MII.get(MI->getOpcode()),
388 O << formatHex(Target);
395 raw_ostream &O) {
396 const MCOperand &MO1 = MI->getOperand(OpNum);
398 MO1.getExpr()->print(O, &MAI);
402 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
403 O << "[pc, ";
408 // Special value for #-0. All others are normal.
412 markup(O, Markup::Immediate) << "#-" << formatImm(-OffImm);
414 markup(O, Markup::Immediate) << "#" << formatImm(OffImm);
416 O << "]";
419 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
420 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
421 // REG 0 0 - e.g. R5
422 // REG REG 0,SH_OPC - e.g. R5, ROR R3
423 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
426 raw_ostream &O) {
427 const MCOperand &MO1 = MI->getOperand(OpNum);
428 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
429 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
431 printRegName(O, MO1.getReg());
435 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
439 O << ' ';
440 printRegName(O, MO2.getReg());
446 raw_ostream &O) {
447 const MCOperand &MO1 = MI->getOperand(OpNum);
448 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
450 printRegName(O, MO1.getReg());
453 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
457 //===--------------------------------------------------------------------===//
459 //===--------------------------------------------------------------------===//
463 raw_ostream &O) {
464 const MCOperand &MO1 = MI->getOperand(Op);
465 const MCOperand &MO2 = MI->getOperand(Op + 1);
466 const MCOperand &MO3 = MI->getOperand(Op + 2);
468 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
469 O << "[";
470 printRegName(O, MO1.getReg());
474 O << ", ";
475 markup(O, Markup::Immediate)
479 O << "]";
483 O << ", ";
484 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
485 printRegName(O, MO2.getReg());
487 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
489 O << "]";
494 raw_ostream &O) {
495 const MCOperand &MO1 = MI->getOperand(Op);
496 const MCOperand &MO2 = MI->getOperand(Op + 1);
498 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
499 O << "[";
500 printRegName(O, MO1.getReg());
501 O << ", ";
502 printRegName(O, MO2.getReg());
503 O << "]";
508 raw_ostream &O) {
509 const MCOperand &MO1 = MI->getOperand(Op);
510 const MCOperand &MO2 = MI->getOperand(Op + 1);
511 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
512 O << "[";
513 printRegName(O, MO1.getReg());
514 O << ", ";
515 printRegName(O, MO2.getReg());
516 O << ", lsl ";
517 markup(O, Markup::Immediate) << "#1";
518 O << "]";
523 raw_ostream &O) {
524 const MCOperand &MO1 = MI->getOperand(Op);
527 printOperand(MI, Op, STI, O);
532 const MCOperand &MO3 = MI->getOperand(Op + 2);
537 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
543 raw_ostream &O) {
544 const MCOperand &MO1 = MI->getOperand(OpNum);
545 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
549 markup(O, Markup::Immediate)
555 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
556 printRegName(O, MO1.getReg());
558 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
562 //===--------------------------------------------------------------------===//
564 //===--------------------------------------------------------------------===//
567 raw_ostream &O,
569 const MCOperand &MO1 = MI->getOperand(Op);
570 const MCOperand &MO2 = MI->getOperand(Op + 1);
571 const MCOperand &MO3 = MI->getOperand(Op + 2);
573 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
574 O << '[';
575 printRegName(O, MO1.getReg());
578 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
579 printRegName(O, MO2.getReg());
580 O << ']';
589 O << ", ";
590 markup(O, Markup::Immediate) << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs;
592 O << ']';
598 raw_ostream &O) {
599 const MCOperand &MO1 = MI->getOperand(Op);
601 printOperand(MI, Op, STI, O);
605 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
608 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
614 raw_ostream &O) {
615 const MCOperand &MO1 = MI->getOperand(OpNum);
616 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
619 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
620 printRegName(O, MO1.getReg());
625 markup(O, Markup::Immediate)
632 raw_ostream &O) {
633 const MCOperand &MO = MI->getOperand(OpNum);
635 markup(O, Markup::Immediate)
636 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
641 raw_ostream &O) {
642 const MCOperand &MO1 = MI->getOperand(OpNum);
643 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
645 O << (MO2.getImm() ? "" : "-");
646 printRegName(O, MO1.getReg());
651 raw_ostream &O) {
652 const MCOperand &MO = MI->getOperand(OpNum);
654 markup(O, Markup::Immediate)
655 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
661 raw_ostream &O) {
662 const MCOperand &MO1 = MI->getOperand(OpNum);
663 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
665 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
666 O << "[";
667 printRegName(O, MO1.getReg());
668 O << ", ";
669 printRegName(O, MO2.getReg());
672 printRegImmShift(O, ARM_AM::uxtw, shift, *this);
674 O << "]";
679 raw_ostream &O) {
681 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
682 O << ARM_AM::getAMSubModeStr(Mode);
688 raw_ostream &O) {
689 const MCOperand &MO1 = MI->getOperand(OpNum);
690 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
693 printOperand(MI, OpNum, STI, O);
697 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
698 O << "[";
699 printRegName(O, MO1.getReg());
704 O << ", ";
705 markup(O, Markup::Immediate)
708 O << "]";
714 raw_ostream &O) {
715 const MCOperand &MO1 = MI->getOperand(OpNum);
716 const MCOperand &MO2 = MI->getOperand(OpNum+1);
719 printOperand(MI, OpNum, STI, O);
723 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
724 O << "[";
725 printRegName(O, MO1.getReg());
730 O << ", ";
731 markup(O, Markup::Immediate)
735 O << "]";
740 raw_ostream &O) {
741 const MCOperand &MO1 = MI->getOperand(OpNum);
742 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
744 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
745 O << "[";
746 printRegName(O, MO1.getReg());
748 O << ":" << (MO2.getImm() << 3);
750 O << "]";
755 raw_ostream &O) {
756 const MCOperand &MO1 = MI->getOperand(OpNum);
757 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
758 O << "[";
759 printRegName(O, MO1.getReg());
760 O << "]";
766 raw_ostream &O) {
767 const MCOperand &MO = MI->getOperand(OpNum);
769 O << "!";
771 O << ", ";
772 printRegName(O, MO.getReg());
779 raw_ostream &O) {
780 const MCOperand &MO = MI->getOperand(OpNum);
783 int32_t width = llvm::bit_width(v) - lsb;
785 markup(O, Markup::Immediate) << '#' << lsb;
786 O << ", ";
787 markup(O, Markup::Immediate) << '#' << width;
792 raw_ostream &O) {
793 unsigned val = MI->getOperand(OpNum).getImm();
794 O << ARM_MB::MemBOptToString(val, STI.hasFeature(ARM::HasV8Ops));
799 raw_ostream &O) {
800 unsigned val = MI->getOperand(OpNum).getImm();
801 O << ARM_ISB::InstSyncBOptToString(val);
806 raw_ostream &O) {
807 unsigned val = MI->getOperand(OpNum).getImm();
808 O << ARM_TSB::TraceSyncBOptToString(val);
813 raw_ostream &O) {
814 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
818 O << ", asr ";
819 markup(O, Markup::Immediate) << "#" << (Amt == 0 ? 32 : Amt);
821 O << ", lsl ";
822 markup(O, Markup::Immediate) << "#" << Amt;
828 raw_ostream &O) {
829 unsigned Imm = MI->getOperand(OpNum).getImm();
833 O << ", lsl ";
834 markup(O, Markup::Immediate) << "#" << Imm;
839 raw_ostream &O) {
840 unsigned Imm = MI->getOperand(OpNum).getImm();
845 O << ", asr ";
846 markup(O, Markup::Immediate) << "#" << Imm;
851 raw_ostream &O) {
852 if (MI->getOpcode() != ARM::t2CLRM && MI->getOpcode() != ARM::VSCCLRMS) {
860 O << "{";
861 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
863 O << ", ";
864 printRegName(O, MI->getOperand(i).getReg());
866 O << "}";
871 raw_ostream &O) {
872 MCRegister Reg = MI->getOperand(OpNum).getReg();
873 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
874 O << ", ";
875 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
880 raw_ostream &O) {
881 const MCOperand &Op = MI->getOperand(OpNum);
883 O << "be";
885 O << "le";
889 const MCSubtargetInfo &STI, raw_ostream &O) {
890 const MCOperand &Op = MI->getOperand(OpNum);
891 O << ARM_PROC::IModToString(Op.getImm());
895 const MCSubtargetInfo &STI, raw_ostream &O) {
896 const MCOperand &Op = MI->getOperand(OpNum);
898 for (int i = 2; i >= 0; --i)
900 O << ARM_PROC::IFlagsToString(1 << i);
903 O << "none";
908 raw_ostream &O) {
909 const MCOperand &Op = MI->getOperand(OpNum);
913 unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
914 unsigned Opcode = MI->getOpcode();
919 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
920 O << TheReg->Name;
925 // Handle the basic 8-bit mask.
928 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
932 O << TheReg->Name;
939 O << TheReg->Name;
943 O << SYSm;
954 O << "APSR_";
959 O << "g";
962 O << "nzcvq";
965 O << "nzcvqg";
971 O << "SPSR";
973 O << "CPSR";
976 O << '_';
978 O << 'f';
980 O << 's';
982 O << 'x';
984 O << 'c';
990 raw_ostream &O) {
991 uint32_t Banked = MI->getOperand(OpNum).getImm();
994 std::string Name = TheReg->Name;
999 O << Name;
1004 raw_ostream &O) {
1005 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1008 O << "<und>";
1010 O << ARMCondCodeToString(CC);
1015 raw_ostream &O) {
1016 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
1017 O << "cs";
1019 printMandatoryPredicateOperand(MI, OpNum, STI, O);
1025 raw_ostream &O) {
1026 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1027 O << ARMCondCodeToString(CC);
1033 raw_ostream &O) {
1034 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1035 O << ARMCondCodeToString(ARMCC::getOppositeCondition(CC));
1040 raw_ostream &O) {
1041 if (MI->getOperand(OpNum).getReg()) {
1042 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1044 O << 's';
1050 raw_ostream &O) {
1051 O << MI->getOperand(OpNum).getImm();
1056 raw_ostream &O) {
1057 O << "p" << MI->getOperand(OpNum).getImm();
1062 raw_ostream &O) {
1063 O << "c" << MI->getOperand(OpNum).getImm();
1068 raw_ostream &O) {
1069 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1073 const MCSubtargetInfo &STI, raw_ostream &O) {
1074 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1080 raw_ostream &O) {
1081 const MCOperand &MO = MI->getOperand(OpNum);
1084 MO.getExpr()->print(O, &MAI);
1090 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1092 O << "#-0";
1094 O << "#-" << -OffImm;
1096 O << "#" << OffImm;
1101 raw_ostream &O) {
1102 markup(O, Markup::Immediate)
1103 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4);
1108 raw_ostream &O) {
1109 unsigned Imm = MI->getOperand(OpNum).getImm();
1110 markup(O, Markup::Immediate) << "#" << formatImm((Imm == 0 ? 32 : Imm));
1115 raw_ostream &O) {
1116 // (3 - the number of trailing zeros) is the number of then / else.
1117 unsigned Mask = MI->getOperand(OpNum).getImm();
1120 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1122 O << 'e';
1124 O << 't';
1130 raw_ostream &O) {
1131 const MCOperand &MO1 = MI->getOperand(Op);
1132 const MCOperand &MO2 = MI->getOperand(Op + 1);
1135 printOperand(MI, Op, STI, O);
1139 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1140 O << "[";
1141 printRegName(O, MO1.getReg());
1143 O << ", ";
1144 printRegName(O, RegNum);
1146 O << "]";
1152 raw_ostream &O,
1154 const MCOperand &MO1 = MI->getOperand(Op);
1155 const MCOperand &MO2 = MI->getOperand(Op + 1);
1158 printOperand(MI, Op, STI, O);
1162 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1163 O << "[";
1164 printRegName(O, MO1.getReg());
1166 O << ", ";
1167 markup(O, Markup::Immediate) << "#" << formatImm(ImmOffs * Scale);
1169 O << "]";
1175 raw_ostream &O) {
1176 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1182 raw_ostream &O) {
1183 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1189 raw_ostream &O) {
1190 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1195 raw_ostream &O) {
1196 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1199 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1201 // REG 0 0 - e.g. R5
1202 // REG IMM, SH_OPC - e.g. R5, LSL #3
1205 raw_ostream &O) {
1206 const MCOperand &MO1 = MI->getOperand(OpNum);
1207 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1210 printRegName(O, Reg);
1214 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1221 raw_ostream &O) {
1222 const MCOperand &MO1 = MI->getOperand(OpNum);
1223 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1226 printOperand(MI, OpNum, STI, O);
1230 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1231 O << "[";
1232 printRegName(O, MO1.getReg());
1236 // Special value for #-0. All others are normal.
1240 O << ", ";
1241 markup(O, Markup::Immediate) << "#-" << formatImm(-OffImm);
1243 O << ", ";
1244 markup(O, Markup::Immediate) << "#" << formatImm(OffImm);
1246 O << "]";
1253 raw_ostream &O) {
1254 const MCOperand &MO1 = MI->getOperand(OpNum);
1255 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1257 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1258 O << "[";
1259 printRegName(O, MO1.getReg());
1267 O << ", ";
1268 markup(O, Markup::Immediate) << "#-" << -OffImm;
1270 O << ", ";
1271 markup(O, Markup::Immediate) << "#" << OffImm;
1273 O << "]";
1280 raw_ostream &O) {
1281 const MCOperand &MO1 = MI->getOperand(OpNum);
1282 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1285 printOperand(MI, OpNum, STI, O);
1289 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1290 O << "[";
1291 printRegName(O, MO1.getReg());
1302 O << ", ";
1303 markup(O, Markup::Immediate) << "#-" << -OffImm;
1305 O << ", ";
1306 markup(O, Markup::Immediate) << "#" << OffImm;
1308 O << "]";
1313 raw_ostream &O) {
1314 const MCOperand &MO1 = MI->getOperand(OpNum);
1315 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1317 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1318 O << "[";
1319 printRegName(O, MO1.getReg());
1321 O << ", ";
1322 markup(O, Markup::Immediate) << "#" << formatImm(MO2.getImm() * 4);
1324 O << "]";
1329 raw_ostream &O) {
1330 const MCOperand &MO1 = MI->getOperand(OpNum);
1332 O << ", ";
1333 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1335 O << "#-0";
1337 O << "#-" << -OffImm;
1339 O << "#" << OffImm;
1344 raw_ostream &O) {
1345 const MCOperand &MO1 = MI->getOperand(OpNum);
1350 O << ", ";
1351 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1353 O << "#-0";
1355 O << "#-" << -OffImm;
1357 O << "#" << OffImm;
1363 raw_ostream &O) {
1364 const MCOperand &MO1 = MI->getOperand(OpNum);
1365 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1366 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1368 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1369 O << "[";
1370 printRegName(O, MO1.getReg());
1373 O << ", ";
1374 printRegName(O, MO2.getReg());
1379 O << ", lsl ";
1380 markup(O, Markup::Immediate) << "#" << ShAmt;
1382 O << "]";
1387 raw_ostream &O) {
1388 const MCOperand &MO = MI->getOperand(OpNum);
1389 markup(O, Markup::Immediate) << '#' << ARM_AM::getFPImmFloat(MO.getImm());
1394 raw_ostream &O) {
1395 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1399 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1400 O << "#0x";
1401 O.write_hex(Val);
1406 raw_ostream &O) {
1407 unsigned Imm = MI->getOperand(OpNum).getImm();
1408 markup(O, Markup::Immediate) << "#" << formatImm(Imm + 1);
1413 raw_ostream &O) {
1414 unsigned Imm = MI->getOperand(OpNum).getImm();
1418 O << ", ror ";
1419 markup(O, Markup::Immediate) << "#" << 8 * Imm;
1424 raw_ostream &O) {
1425 MCOperand Op = MI->getOperand(OpNum);
1429 return printOperand(MI, OpNum, STI, O);
1435 switch (MI->getOpcode()) {
1438 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1449 O << "#";
1451 markup(O, Markup::Immediate) << static_cast<uint32_t>(Rotated);
1453 markup(O, Markup::Immediate) << Rotated;
1458 O << "#";
1459 markup(O, Markup::Immediate) << Bits;
1460 O << ", #";
1461 markup(O, Markup::Immediate) << Rot;
1465 const MCSubtargetInfo &STI, raw_ostream &O) {
1466 markup(O, Markup::Immediate) << "#" << 16 - MI->getOperand(OpNum).getImm();
1470 const MCSubtargetInfo &STI, raw_ostream &O) {
1471 markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
1476 raw_ostream &O) {
1477 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1482 raw_ostream &O) {
1483 O << "{";
1484 printRegName(O, MI->getOperand(OpNum).getReg());
1485 O << "}";
1490 raw_ostream &O) {
1491 MCRegister Reg = MI->getOperand(OpNum).getReg();
1494 O << "{";
1495 printRegName(O, Reg0);
1496 O << ", ";
1497 printRegName(O, Reg1);
1498 O << "}";
1503 raw_ostream &O) {
1504 MCRegister Reg = MI->getOperand(OpNum).getReg();
1507 O << "{";
1508 printRegName(O, Reg0);
1509 O << ", ";
1510 printRegName(O, Reg1);
1511 O << "}";
1516 raw_ostream &O) {
1520 O << "{";
1521 printRegName(O, MI->getOperand(OpNum).getReg());
1522 O << ", ";
1523 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1524 O << ", ";
1525 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1526 O << "}";
1531 raw_ostream &O) {
1535 O << "{";
1536 printRegName(O, MI->getOperand(OpNum).getReg());
1537 O << ", ";
1538 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1539 O << ", ";
1540 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1541 O << ", ";
1542 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1543 O << "}";
1549 raw_ostream &O) {
1550 O << "{";
1551 printRegName(O, MI->getOperand(OpNum).getReg());
1552 O << "[]}";
1558 raw_ostream &O) {
1559 MCRegister Reg = MI->getOperand(OpNum).getReg();
1562 O << "{";
1563 printRegName(O, Reg0);
1564 O << "[], ";
1565 printRegName(O, Reg1);
1566 O << "[]}";
1572 raw_ostream &O) {
1576 O << "{";
1577 printRegName(O, MI->getOperand(OpNum).getReg());
1578 O << "[], ";
1579 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1580 O << "[], ";
1581 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1582 O << "[]}";
1588 raw_ostream &O) {
1592 O << "{";
1593 printRegName(O, MI->getOperand(OpNum).getReg());
1594 O << "[], ";
1595 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1596 O << "[], ";
1597 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1598 O << "[], ";
1599 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1600 O << "[]}";
1605 raw_ostream &O) {
1606 MCRegister Reg = MI->getOperand(OpNum).getReg();
1609 O << "{";
1610 printRegName(O, Reg0);
1611 O << "[], ";
1612 printRegName(O, Reg1);
1613 O << "[]}";
1618 raw_ostream &O) {
1622 O << "{";
1623 printRegName(O, MI->getOperand(OpNum).getReg());
1624 O << "[], ";
1625 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1626 O << "[], ";
1627 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1628 O << "[]}";
1633 raw_ostream &O) {
1637 O << "{";
1638 printRegName(O, MI->getOperand(OpNum).getReg());
1639 O << "[], ";
1640 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1641 O << "[], ";
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1643 O << "[], ";
1644 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1645 O << "[]}";
1651 raw_ostream &O) {
1655 O << "{";
1656 printRegName(O, MI->getOperand(OpNum).getReg());
1657 O << ", ";
1658 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1659 O << ", ";
1660 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1661 O << "}";
1666 raw_ostream &O) {
1670 O << "{";
1671 printRegName(O, MI->getOperand(OpNum).getReg());
1672 O << ", ";
1673 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1674 O << ", ";
1675 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1676 O << ", ";
1677 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1678 O << "}";
1684 raw_ostream &O) {
1685 MCRegister Reg = MI->getOperand(OpNum).getReg();
1688 O << Prefix;
1689 printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));
1692 O << "}";
1698 raw_ostream &O) {
1699 unsigned Val = MI->getOperand(OpNo).getImm();
1700 O << "#" << (Val * Angle) + Remainder;
1705 raw_ostream &O) {
1706 ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
1708 O << ARMVPTPredToString(CC);
1713 raw_ostream &O) {
1714 // (3 - the number of trailing zeroes) is the number of them / else.
1715 unsigned Mask = MI->getOperand(OpNum).getImm();
1718 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1721 O << 't';
1723 O << 'e';
1729 raw_ostream &O) {
1730 uint32_t Val = MI->getOperand(OpNum).getImm();
1732 O << "#" << (Val == 1 ? 48 : 64);