Lines Matching defs:OpNum
380 unsigned OpNum, const MCSubtargetInfo &STI,
382 const MCOperand &Op = MI->getOperand(OpNum);
384 return printOperand(MI, OpNum, STI, O);
393 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
396 const MCOperand &MO1 = MI->getOperand(OpNum);
424 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
427 const MCOperand &MO1 = MI->getOperand(OpNum);
428 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
429 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
444 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
447 const MCOperand &MO1 = MI->getOperand(OpNum);
448 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
541 unsigned OpNum,
544 const MCOperand &MO1 = MI->getOperand(OpNum);
545 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
612 unsigned OpNum,
615 const MCOperand &MO1 = MI->getOperand(OpNum);
616 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
630 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
633 const MCOperand &MO = MI->getOperand(OpNum);
639 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
642 const MCOperand &MO1 = MI->getOperand(OpNum);
643 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
649 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
652 const MCOperand &MO = MI->getOperand(OpNum);
659 void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
662 const MCOperand &MO1 = MI->getOperand(OpNum);
663 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
677 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
681 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
686 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
689 const MCOperand &MO1 = MI->getOperand(OpNum);
690 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
693 printOperand(MI, OpNum, STI, O);
712 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
715 const MCOperand &MO1 = MI->getOperand(OpNum);
716 const MCOperand &MO2 = MI->getOperand(OpNum+1);
719 printOperand(MI, OpNum, STI, O);
738 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
741 const MCOperand &MO1 = MI->getOperand(OpNum);
742 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
753 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
756 const MCOperand &MO1 = MI->getOperand(OpNum);
764 unsigned OpNum,
767 const MCOperand &MO = MI->getOperand(OpNum);
777 unsigned OpNum,
780 const MCOperand &MO = MI->getOperand(OpNum);
790 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
793 unsigned val = MI->getOperand(OpNum).getImm();
797 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
800 unsigned val = MI->getOperand(OpNum).getImm();
804 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
807 unsigned val = MI->getOperand(OpNum).getImm();
811 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
814 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
826 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
829 unsigned Imm = MI->getOperand(OpNum).getImm();
837 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
840 unsigned Imm = MI->getOperand(OpNum).getImm();
849 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
853 assert(is_sorted(drop_begin(*MI, OpNum),
861 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
862 if (i != OpNum)
869 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
872 MCRegister Reg = MI->getOperand(OpNum).getReg();
878 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
881 const MCOperand &Op = MI->getOperand(OpNum);
888 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
890 const MCOperand &Op = MI->getOperand(OpNum);
894 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
896 const MCOperand &Op = MI->getOperand(OpNum);
906 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
909 const MCOperand &Op = MI->getOperand(OpNum);
988 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
991 uint32_t Banked = MI->getOperand(OpNum).getImm();
1002 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
1005 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1014 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1016 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
1019 printMandatoryPredicateOperand(MI, OpNum, STI, O);
1023 unsigned OpNum,
1026 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1031 unsigned OpNum,
1034 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1038 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1041 if (MI->getOperand(OpNum).getReg()) {
1042 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1048 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1051 O << MI->getOperand(OpNum).getImm();
1054 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1057 O << "p" << MI->getOperand(OpNum).getImm();
1060 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1063 O << "c" << MI->getOperand(OpNum).getImm();
1066 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1069 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1072 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1078 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1081 const MCOperand &MO = MI->getOperand(OpNum);
1099 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1103 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4);
1106 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1109 unsigned Imm = MI->getOperand(OpNum).getImm();
1113 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1117 unsigned Mask = MI->getOperand(OpNum).getImm();
1203 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1206 const MCOperand &MO1 = MI->getOperand(OpNum);
1207 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1219 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1222 const MCOperand &MO1 = MI->getOperand(OpNum);
1223 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1226 printOperand(MI, OpNum, STI, O);
1251 unsigned OpNum,
1254 const MCOperand &MO1 = MI->getOperand(OpNum);
1255 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1278 unsigned OpNum,
1281 const MCOperand &MO1 = MI->getOperand(OpNum);
1282 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1285 printOperand(MI, OpNum, STI, O);
1312 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1314 const MCOperand &MO1 = MI->getOperand(OpNum);
1315 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1328 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1330 const MCOperand &MO1 = MI->getOperand(OpNum);
1343 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1345 const MCOperand &MO1 = MI->getOperand(OpNum);
1361 unsigned OpNum,
1364 const MCOperand &MO1 = MI->getOperand(OpNum);
1365 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1366 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1385 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1388 const MCOperand &MO = MI->getOperand(OpNum);
1392 void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
1395 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1404 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1407 unsigned Imm = MI->getOperand(OpNum).getImm();
1411 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1414 unsigned Imm = MI->getOperand(OpNum).getImm();
1422 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1425 MCOperand Op = MI->getOperand(OpNum);
1429 return printOperand(MI, OpNum, STI, O);
1438 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1464 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1466 markup(O, Markup::Immediate) << "#" << 16 - MI->getOperand(OpNum).getImm();
1469 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1471 markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
1474 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1477 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1480 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1484 printRegName(O, MI->getOperand(OpNum).getReg());
1488 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1491 MCRegister Reg = MI->getOperand(OpNum).getReg();
1501 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1504 MCRegister Reg = MI->getOperand(OpNum).getReg();
1514 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1521 printRegName(O, MI->getOperand(OpNum).getReg());
1523 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1525 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1529 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1536 printRegName(O, MI->getOperand(OpNum).getReg());
1538 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1540 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1542 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1547 unsigned OpNum,
1551 printRegName(O, MI->getOperand(OpNum).getReg());
1556 unsigned OpNum,
1559 MCRegister Reg = MI->getOperand(OpNum).getReg();
1570 unsigned OpNum,
1577 printRegName(O, MI->getOperand(OpNum).getReg());
1579 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1581 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1586 unsigned OpNum,
1593 printRegName(O, MI->getOperand(OpNum).getReg());
1595 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1597 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1599 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1604 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1606 MCRegister Reg = MI->getOperand(OpNum).getReg();
1617 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1623 printRegName(O, MI->getOperand(OpNum).getReg());
1625 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1627 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1632 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1638 printRegName(O, MI->getOperand(OpNum).getReg());
1640 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1644 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1649 unsigned OpNum,
1656 printRegName(O, MI->getOperand(OpNum).getReg());
1658 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1660 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1664 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1671 printRegName(O, MI->getOperand(OpNum).getReg());
1673 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1675 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1677 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1682 void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
1685 MCRegister Reg = MI->getOperand(OpNum).getReg();
1703 void ARMInstPrinter::printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
1706 ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
1711 void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
1715 unsigned Mask = MI->getOperand(OpNum).getImm();
1727 void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
1730 uint32_t Val = MI->getOperand(OpNum).getImm();