Lines Matching defs:MI
86 void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
89 unsigned Opcode = MI->getOpcode();
93 const MCOperand &Reg = MI->getOperand(0);
101 const MCOperand &Reg = MI->getOperand(0);
109 const MCOperand &Reg = MI->getOperand(0);
117 const MCOperand &Reg = MI->getOperand(0);
127 const MCOperand &Dst = MI->getOperand(0);
128 const MCOperand &MO1 = MI->getOperand(1);
129 const MCOperand &MO2 = MI->getOperand(2);
130 const MCOperand &MO3 = MI->getOperand(3);
133 printSBitModifierOperand(MI, 6, STI, O);
134 printPredicateOperand(MI, 4, STI, O);
150 const MCOperand &Dst = MI->getOperand(0);
151 const MCOperand &MO1 = MI->getOperand(1);
152 const MCOperand &MO2 = MI->getOperand(2);
155 printSBitModifierOperand(MI, 5, STI, O);
156 printPredicateOperand(MI, 3, STI, O);
178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
181 printPredicateOperand(MI, 2, STI, O);
185 printRegisterList(MI, 4, STI, O);
192 if (MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(3).getImm() == -4) {
195 printPredicateOperand(MI, 4, STI, O);
197 printRegName(O, MI->getOperand(1).getReg());
207 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
210 printPredicateOperand(MI, 2, STI, O);
214 printRegisterList(MI, 4, STI, O);
221 if (MI->getOperand(2).getReg() == ARM::SP &&
222 MI->getOperand(4).getImm() == 4) {
224 printPredicateOperand(MI, 5, STI, O);
226 printRegName(O, MI->getOperand(0).getReg());
236 if (MI->getOperand(0).getReg() == ARM::SP) {
238 printPredicateOperand(MI, 2, STI, O);
240 printRegisterList(MI, 4, STI, O);
249 if (MI->getOperand(0).getReg() == ARM::SP) {
251 printPredicateOperand(MI, 2, STI, O);
253 printRegisterList(MI, 4, STI, O);
261 MCRegister BaseReg = MI->getOperand(0).getReg();
262 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
263 if (MI->getOperand(i).getReg() == BaseReg)
269 printPredicateOperand(MI, 1, STI, O);
275 printRegisterList(MI, 3, STI, O);
292 MCRegister Reg = MI->getOperand(isStore ? 1 : 0).getReg();
299 NewMI.addOperand(MI->getOperand(0));
305 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
306 NewMI.addOperand(MI->getOperand(i));
317 switch (MI->getOperand(0).getImm()) {
319 if (!printAliasInstr(MI, Address, STI, O))
320 printInstruction(MI, Address, STI, O);
333 if (!printAliasInstr(MI, Address, STI, O))
334 printInstruction(MI, Address, STI, O);
339 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
341 const MCOperand &Op = MI->getOperand(OpNo);
379 void ARMInstPrinter::printOperand(const MCInst *MI, uint64_t Address,
382 const MCOperand &Op = MI->getOperand(OpNum);
384 return printOperand(MI, OpNum, STI, O);
385 uint64_t Target = ARM_MC::evaluateBranchTarget(MII.get(MI->getOpcode()),
393 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
396 const MCOperand &MO1 = MI->getOperand(OpNum);
424 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
427 const MCOperand &MO1 = MI->getOperand(OpNum);
428 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
429 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
444 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
447 const MCOperand &MO1 = MI->getOperand(OpNum);
448 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
461 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
464 const MCOperand &MO1 = MI->getOperand(Op);
465 const MCOperand &MO2 = MI->getOperand(Op + 1);
466 const MCOperand &MO3 = MI->getOperand(Op + 2);
492 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
495 const MCOperand &MO1 = MI->getOperand(Op);
496 const MCOperand &MO2 = MI->getOperand(Op + 1);
506 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
509 const MCOperand &MO1 = MI->getOperand(Op);
510 const MCOperand &MO2 = MI->getOperand(Op + 1);
521 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
524 const MCOperand &MO1 = MI->getOperand(Op);
527 printOperand(MI, Op, STI, O);
532 const MCOperand &MO3 = MI->getOperand(Op + 2);
537 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
540 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
544 const MCOperand &MO1 = MI->getOperand(OpNum);
545 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
566 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
569 const MCOperand &MO1 = MI->getOperand(Op);
570 const MCOperand &MO2 = MI->getOperand(Op + 1);
571 const MCOperand &MO3 = MI->getOperand(Op + 2);
596 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
599 const MCOperand &MO1 = MI->getOperand(Op);
601 printOperand(MI, Op, STI, O);
605 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
608 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
611 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
615 const MCOperand &MO1 = MI->getOperand(OpNum);
616 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
630 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
633 const MCOperand &MO = MI->getOperand(OpNum);
639 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
642 const MCOperand &MO1 = MI->getOperand(OpNum);
643 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
649 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
652 const MCOperand &MO = MI->getOperand(OpNum);
659 void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
662 const MCOperand &MO1 = MI->getOperand(OpNum);
663 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
677 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
681 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
686 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
689 const MCOperand &MO1 = MI->getOperand(OpNum);
690 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
693 printOperand(MI, OpNum, STI, O);
712 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
715 const MCOperand &MO1 = MI->getOperand(OpNum);
716 const MCOperand &MO2 = MI->getOperand(OpNum+1);
719 printOperand(MI, OpNum, STI, O);
738 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
741 const MCOperand &MO1 = MI->getOperand(OpNum);
742 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
753 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
756 const MCOperand &MO1 = MI->getOperand(OpNum);
763 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
767 const MCOperand &MO = MI->getOperand(OpNum);
776 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
780 const MCOperand &MO = MI->getOperand(OpNum);
790 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
793 unsigned val = MI->getOperand(OpNum).getImm();
797 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
800 unsigned val = MI->getOperand(OpNum).getImm();
804 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
807 unsigned val = MI->getOperand(OpNum).getImm();
811 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
814 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
826 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
829 unsigned Imm = MI->getOperand(OpNum).getImm();
837 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
840 unsigned Imm = MI->getOperand(OpNum).getImm();
849 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
852 if (MI->getOpcode() != ARM::t2CLRM && MI->getOpcode() != ARM::VSCCLRMS) {
853 assert(is_sorted(drop_begin(*MI, OpNum),
861 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
864 printRegName(O, MI->getOperand(i).getReg());
869 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
872 MCRegister Reg = MI->getOperand(OpNum).getReg();
878 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
881 const MCOperand &Op = MI->getOperand(OpNum);
888 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
890 const MCOperand &Op = MI->getOperand(OpNum);
894 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
896 const MCOperand &Op = MI->getOperand(OpNum);
906 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
909 const MCOperand &Op = MI->getOperand(OpNum);
914 unsigned Opcode = MI->getOpcode();
988 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
991 uint32_t Banked = MI->getOperand(OpNum).getImm();
1002 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
1005 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1014 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1016 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
1019 printMandatoryPredicateOperand(MI, OpNum, STI, O);
1022 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1026 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1030 void ARMInstPrinter::printMandatoryInvertedPredicateOperand(const MCInst *MI,
1034 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1038 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1041 if (MI->getOperand(OpNum).getReg()) {
1042 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1048 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1051 O << MI->getOperand(OpNum).getImm();
1054 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1057 O << "p" << MI->getOperand(OpNum).getImm();
1060 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1063 O << "c" << MI->getOperand(OpNum).getImm();
1066 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1069 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1072 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1078 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1081 const MCOperand &MO = MI->getOperand(OpNum);
1099 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1103 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4);
1106 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1109 unsigned Imm = MI->getOperand(OpNum).getImm();
1113 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1117 unsigned Mask = MI->getOperand(OpNum).getImm();
1128 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1131 const MCOperand &MO1 = MI->getOperand(Op);
1132 const MCOperand &MO2 = MI->getOperand(Op + 1);
1135 printOperand(MI, Op, STI, O);
1149 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1154 const MCOperand &MO1 = MI->getOperand(Op);
1155 const MCOperand &MO2 = MI->getOperand(Op + 1);
1158 printOperand(MI, Op, STI, O);
1172 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1176 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1179 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1183 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1186 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1190 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1193 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1196 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1203 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1206 const MCOperand &MO1 = MI->getOperand(OpNum);
1207 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1219 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1222 const MCOperand &MO1 = MI->getOperand(OpNum);
1223 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1226 printOperand(MI, OpNum, STI, O);
1250 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1254 const MCOperand &MO1 = MI->getOperand(OpNum);
1255 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1277 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1281 const MCOperand &MO1 = MI->getOperand(OpNum);
1282 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1285 printOperand(MI, OpNum, STI, O);
1312 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1314 const MCOperand &MO1 = MI->getOperand(OpNum);
1315 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1328 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1330 const MCOperand &MO1 = MI->getOperand(OpNum);
1343 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1345 const MCOperand &MO1 = MI->getOperand(OpNum);
1360 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1364 const MCOperand &MO1 = MI->getOperand(OpNum);
1365 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1366 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1385 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1388 const MCOperand &MO = MI->getOperand(OpNum);
1392 void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
1395 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1404 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1407 unsigned Imm = MI->getOperand(OpNum).getImm();
1411 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1414 unsigned Imm = MI->getOperand(OpNum).getImm();
1422 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1425 MCOperand Op = MI->getOperand(OpNum);
1429 return printOperand(MI, OpNum, STI, O);
1435 switch (MI->getOpcode()) {
1438 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1464 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1466 markup(O, Markup::Immediate) << "#" << 16 - MI->getOperand(OpNum).getImm();
1469 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1471 markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
1474 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1477 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1480 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1484 printRegName(O, MI->getOperand(OpNum).getReg());
1488 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1491 MCRegister Reg = MI->getOperand(OpNum).getReg();
1501 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1504 MCRegister Reg = MI->getOperand(OpNum).getReg();
1514 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1521 printRegName(O, MI->getOperand(OpNum).getReg());
1523 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1525 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1529 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1536 printRegName(O, MI->getOperand(OpNum).getReg());
1538 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1540 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1542 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1546 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1551 printRegName(O, MI->getOperand(OpNum).getReg());
1555 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1559 MCRegister Reg = MI->getOperand(OpNum).getReg();
1569 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1577 printRegName(O, MI->getOperand(OpNum).getReg());
1579 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1581 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1585 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1593 printRegName(O, MI->getOperand(OpNum).getReg());
1595 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1597 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1599 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1604 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1606 MCRegister Reg = MI->getOperand(OpNum).getReg();
1617 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1623 printRegName(O, MI->getOperand(OpNum).getReg());
1625 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1627 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1632 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1638 printRegName(O, MI->getOperand(OpNum).getReg());
1640 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1644 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1648 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1656 printRegName(O, MI->getOperand(OpNum).getReg());
1658 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1660 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1664 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1671 printRegName(O, MI->getOperand(OpNum).getReg());
1673 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1675 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1677 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1682 void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
1685 MCRegister Reg = MI->getOperand(OpNum).getReg();
1696 void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1699 unsigned Val = MI->getOperand(OpNo).getImm();
1703 void ARMInstPrinter::printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
1706 ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
1711 void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
1715 unsigned Mask = MI->getOperand(OpNum).getImm();
1727 void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
1730 uint32_t Val = MI->getOperand(OpNum).getImm();