Lines Matching defs:imm
1674 unsigned imm = fieldFromInstruction(Val, 7, 5);
1696 if (Shift == ARM_AM::ror && imm == 0)
1699 unsigned Op = Shift | (imm << 3);
1877 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1993 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1994 Inst.addOperand(MCOperand::createImm(imm));
2012 imm |= U << 8;
2017 Inst.addOperand(MCOperand::createImm(imm));
2056 unsigned imm = fieldFromInstruction(Insn, 0, 12);
2139 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
2141 Inst.addOperand(MCOperand::createImm(imm));
2144 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
2162 unsigned imm = fieldFromInstruction(Val, 7, 5);
2181 if (ShOp == ARM_AM::ror && imm == 0)
2190 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2192 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2220 unsigned imm = fieldFromInstruction(Insn, 8, 4);
2390 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2654 int imm = fieldFromInstruction(Insn, 0, 8);
2656 if(imm > 4) return MCDisassembler::Fail;
2658 Inst.addOperand(MCOperand::createImm(imm));
2667 unsigned imm = fieldFromInstruction(Insn, 0, 8);
2671 if (imm == 0x0D) {
2673 } else if (imm == 0x1D) {
2675 } else if (imm == 0x2D) {
2677 } else if (imm == 0x0F) {
2683 Inst.addOperand(MCOperand::createImm(imm));
2695 unsigned imm = 0;
2697 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2698 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2699 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2700 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2708 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2709 Inst.addOperand(MCOperand::createImm(imm));
2721 unsigned imm = 0;
2723 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2724 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2733 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2734 Inst.addOperand(MCOperand::createImm(imm));
2828 unsigned imm = fieldFromInstruction(Val, 0, 12);
2834 if (!add) imm *= -1;
2835 if (imm == 0 && !add) imm = INT32_MIN;
2836 Inst.addOperand(MCOperand::createImm(imm));
2838 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2849 // U == 1 to add imm, 0 to subtract it.
2851 unsigned imm = fieldFromInstruction(Val, 0, 8);
2857 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2859 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2870 // U == 1 to add imm, 0 to subtract it.
2872 unsigned imm = fieldFromInstruction(Val, 0, 8);
2878 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2880 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2924 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2928 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2929 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2931 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2935 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2937 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
3762 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3763 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3764 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3765 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3766 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3777 Inst.addOperand(MCOperand::createImm(imm));
3809 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3810 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3811 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3812 imm |= cmode << 8;
3813 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3821 Inst.addOperand(MCOperand::createImm(imm));
3947 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3962 Inst.addOperand(MCOperand::createImm(imm));
4015 unsigned imm = fieldFromInstruction(Val, 3, 5);
4019 Inst.addOperand(MCOperand::createImm(imm));
4027 unsigned imm = Val << 2;
4029 Inst.addOperand(MCOperand::createImm(imm));
4030 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
4051 unsigned imm = fieldFromInstruction(Val, 0, 2);
4069 Inst.addOperand(MCOperand::createImm(imm));
4166 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4167 imm |= (U << 8);
4168 imm |= (Rn << 9);
4238 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4250 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4251 imm |= (Rn << 13);
4319 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4330 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4331 imm |= (Rn << 9);
4358 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4370 int imm = fieldFromInstruction(Insn, 0, 12);
4407 if (imm == 0)
4408 imm = INT32_MIN;
4410 imm = -imm;
4412 Inst.addOperand(MCOperand::createImm(imm));
4422 int imm = Val & 0xFF;
4424 if (!(Val & 0x100)) imm *= -1;
4425 Inst.addOperand(MCOperand::createImm(imm * 4));
4436 int imm = Val & 0x7F;
4439 imm *= -1;
4440 Inst.addOperand(MCOperand::createImm(imm * 4));
4452 unsigned imm = fieldFromInstruction(Val, 0, 9);
4456 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4468 unsigned imm = fieldFromInstruction(Val, 0, 8);
4472 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4484 unsigned imm = fieldFromInstruction(Val, 0, 8);
4489 Inst.addOperand(MCOperand::createImm(imm));
4496 int imm = Val & 0xFF;
4498 imm = INT32_MIN;
4500 imm *= -1;
4501 Inst.addOperand(MCOperand::createImm(imm));
4509 int imm = Val & 0x7F;
4511 imm = INT32_MIN;
4513 imm *= -1;
4514 if (imm != INT32_MIN)
4515 imm *= (1U << shift);
4516 Inst.addOperand(MCOperand::createImm(imm));
4527 unsigned imm = fieldFromInstruction(Val, 0, 9);
4554 imm |= 0x100;
4562 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4575 unsigned imm = fieldFromInstruction(Val, 0, 8);
4579 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4592 unsigned imm = fieldFromInstruction(Val, 0, 8);
4598 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4672 unsigned imm = fieldFromInstruction(Val, 0, 12);
4688 Inst.addOperand(MCOperand::createImm(imm));
4696 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4700 Inst.addOperand(MCOperand::createImm(imm));
4778 int imm = fieldFromInstruction(Insn, 0, 7);
4784 if (imm == 0)
4785 imm = INT32_MIN; // indicate -0
4787 imm *= -1;
4789 if (imm != INT32_MIN)
4790 imm *= (1U << shift);
4791 Inst.addOperand(MCOperand::createImm(imm));
4877 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4878 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4903 unsigned imm = fieldFromInstruction(Val, 0, 8);
4906 Inst.addOperand(MCOperand::createImm(imm));
4909 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4912 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4915 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4916 (imm << 8) | imm));
4922 unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
4923 Inst.addOperand(MCOperand::createImm(imm));
5154 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5155 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5156 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5165 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5180 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5181 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5182 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5193 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5208 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5209 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5210 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5219 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5234 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5235 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5236 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5245 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
6028 unsigned imm = fieldFromInstruction(Insn, 16, 6);
6034 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6035 if (!(imm & 0x38)) {
6066 if (!(imm & 0x20)) return MCDisassembler::Fail;
6072 Inst.addOperand(MCOperand::createImm(64 - imm));
6087 unsigned imm = fieldFromInstruction(Insn, 16, 6);
6093 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6094 if (!(imm & 0x38)) {
6125 if (!(imm & 0x20)) return MCDisassembler::Fail;
6131 Inst.addOperand(MCOperand::createImm(64 - imm));