Lines Matching defs:Vd
1794 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1798 if (regs == 0 || (Vd + regs) > 32) {
1799 regs = Vd + regs > 32 ? 32 - Vd : regs;
1804 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1807 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1819 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1824 if (regs == 0 || (Vd + regs) > MaxReg) {
1825 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
1831 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1834 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
6024 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
6025 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
6068 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
6083 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
6084 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
6127 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
6140 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
6141 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
6153 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
6155 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
6465 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |
6469 unsigned max_reg = Vd + regs;
6474 for (unsigned i = Vd; i < max_sreg; ++i)