Lines Matching defs:Rm
1672 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1677 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1710 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2055 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2160 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2218 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2251 if (type && Rm == 15)
2265 if (!type && Rm == 15)
2278 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2295 if (!type && Rm == 15)
2313 if (!type && (Rt == 15 || Rm == 15))
2390 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2439 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2448 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2749 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2760 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2778 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2953 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2976 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3190 // The fixed offset encodes as Rm == 0xd, so we check for that.
3191 if (Rm == 0xd) {
3221 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3222 // variant encodes Rm == 0xf. Anything else is a register offset post-
3224 if (Rm != 0xD && Rm != 0xF &&
3225 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3308 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3362 if (Rm == 0xF)
3392 if (Rm == 0xD)
3394 else if (Rm != 0xF) {
3395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3577 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3598 if (Rm != 0xF) {
3607 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3608 // variant encodes Rm == 0xf. Anything else is a register offset post-
3610 if (Rm != 0xD && Rm != 0xF &&
3611 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3625 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3651 if (Rm != 0xF)
3658 if (Rm != 0xD && Rm != 0xF) {
3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3674 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3683 if (Rm != 0xF) {
3692 if (Rm == 0xD)
3694 else if (Rm != 0xF) {
3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3710 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3736 if (Rm != 0xF) {
3745 if (Rm == 0xD)
3747 else if (Rm != 0xF) {
3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3863 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3864 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3913 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3914 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3999 unsigned Rm = fieldFromInstruction(Val, 3, 3);
4003 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
4050 unsigned Rm = fieldFromInstruction(Val, 2, 4);
4067 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4720 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4747 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4845 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4850 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5184 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5187 if (Rm == 0xF) S = MCDisassembler::SoftFail;
5258 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5298 if (Rm != 0xF) { // Writeback
5305 if (Rm != 0xF) {
5306 if (Rm != 0xD) {
5307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5325 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5363 if (Rm != 0xF) { // Writeback
5370 if (Rm != 0xF) {
5371 if (Rm != 0xD) {
5372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5390 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5428 if (Rm != 0xF) { // Writeback
5435 if (Rm != 0xF) {
5436 if (Rm != 0xD) {
5437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5457 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5491 if (Rm != 0xF) { // Writeback
5498 if (Rm != 0xF) {
5499 if (Rm != 0xD) {
5500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5520 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5559 if (Rm != 0xF) { // Writeback
5566 if (Rm != 0xF) {
5567 if (Rm != 0xD) {
5568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5590 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5622 if (Rm != 0xF) { // Writeback
5629 if (Rm != 0xF) {
5630 if (Rm != 0xD) {
5631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5653 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5701 if (Rm != 0xF) { // Writeback
5708 if (Rm != 0xF) {
5709 if (Rm != 0xD) {
5710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5734 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5773 if (Rm != 0xF) { // Writeback
5780 if (Rm != 0xF) {
5781 if (Rm != 0xD) {
5782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5806 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5808 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5810 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5813 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5815 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5832 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5834 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5836 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5843 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5845 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
6175 unsigned Rm = fieldFromInstruction(Val, 0, 4);
6176 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
6188 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
6876 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
6907 // Rm, the amount to shift by
6908 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6914 if (Rda == Rm)
6935 // Rm, the amount to shift by
6936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6984 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6985 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))