Lines Matching +full:0 +full:x1e00
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
98 // Position==0 means we're not in an IT block at all. Position==1
99 // means we want the first state bit, which is always 0 (Then).
102 // right bit down to bit 0, including the always-0 bit at bit 4 for
269 // '0' inverse of condition (else).
277 // block. In range [0,4], with 0 being the IT
279 // count of instructions in block. ~0U if no
293 assert(PendingConditionalInsts.size() == 0);
312 ITState.Mask = 0;
313 ITState.CurPosition = ~0U;
316 bool inITBlock() { return ITState.CurPosition != ~0U; }
331 ITState.CurPosition = ~0U; // Done with the IT block after this.
340 unsigned NewMask = 0;
341 NewMask |= ITState.Mask & (0xC << TZ);
342 NewMask |= 0x2 << TZ;
351 ITState.CurPosition = ~0U;
383 unsigned NewMask = 0;
385 NewMask |= ITState.Mask & (0xE << TZ);
410 ITState.CurPosition = 0;
418 bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
423 VPTState.CurPosition = ~0U;
477 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
638 return parsePKHImm(O, ARM_AM::lsl, 0, 31);
704 ITState.CurPosition = ~0U;
706 VPTState.CurPosition = ~0U;
893 unsigned Alignment; // 0 = no alignment specified
1078 return CE->getValue() % 4 == 0;
1087 return CE->getValue() % 2 == 0;
1101 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
1117 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1129 return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1139 int64_t Val = 0;
1155 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1182 return ((Value & 3) == 0) && Value >= N && Value <= M;
1190 return ((Value & 1) == 0) && Value >= N && Value <= M;
1193 return isImmediate<0, 17>();
1217 return isImmediateS4<0, 1020>();
1220 return isImmediateS4<0, 508>();
1227 // explicitly exclude zero. we want that to use the normal 0_508 version.
1228 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1239 if ((CE->getValue() >> 32) > 0) return false;
1241 return Value > 0 && Value < 4096;
1245 return isImmediate<0, 7>();
1289 return Value >= 0 && Value < 65536;
1293 return isImmediate<0, 0xffffff + 1>();
1301 return isImmediate<0, 32>();
1305 return isImmediate<0, 33>();
1364 return Value == 1 || Value == 0;
1436 return Value > 0 && llvm::popcount((uint64_t)Value) == 1 && Value >= Min &&
1463 return 0 < Value && Value < 8;
1483 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1490 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1502 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1514 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1527 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1547 return isMemNoOffset(false, 0);
1551 return isMemNoOffset(false, 0);
1557 return isMemNoOffset(false, 0);
1563 return isMemNoOffset(false, 0);
1569 return isMemNoOffset(false, 0);
1575 return isMemNoOffset(false, 0);
1581 return isMemNoOffset(false, 0);
1587 return isMemNoOffset(false, 0);
1595 return isMemNoOffset(false, 0);
1603 return isMemNoOffset(false, 0);
1613 return isMemNoOffset(false, 0);
1617 if (!isGPRMem() || Memory.Alignment != 0) return false;
1645 if (!isGPRMem() || Memory.Alignment != 0) return false;
1654 // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and
1671 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1682 if (!isGPRMem() || Memory.Alignment != 0) return false;
1689 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1701 if (!isGPRMem() || Memory.Alignment != 0) return false;
1708 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1716 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1724 Memory.Alignment != 0 )
1730 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1737 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1739 // Only lsl #{0, 1, 2, 3} allowed.
1751 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1759 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1761 // Immediate offset, multiple of 4 in range [0, 124].
1765 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1772 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1774 // Immediate offset, multiple of 4 in range [0, 62].
1778 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1785 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1787 // Immediate offset in range [0, 31].
1791 return Val >= 0 && Val <= 31;
1798 Memory.Alignment != 0)
1800 // Immediate offset, multiple of 4 in range [0, 1020].
1804 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1815 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1821 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1822 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1834 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0 ||
1842 // Special case, #-0 is INT32_MIN.
1843 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1849 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1851 // Immediate offset a multiple of 4 in range [0, 1020].
1855 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1861 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1877 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0 ||
1896 if (Val % Divisor != 0)
1907 if (!isMVEMem() || Memory.OffsetImm != nullptr || Memory.Alignment != 0)
1917 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1920 if (shift > 0 &&
1928 if (!isMVEMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1943 if ((Val & ((1U << shift) - 1)) != 0)
1947 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1956 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1958 // Immediate offset in range [0, 255].
1962 return Val >= 0 && Val < 256;
1968 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1977 (Val > -256 && Val < 0);
1983 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
1985 // Immediate offset in range [0, 4095].
1989 return (Val >= 0 && Val < 4096);
2002 if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
2036 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
2287 return Value >= 0 && Value < 256;
2309 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2335 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2336 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2337 return ((Value & 0xffffffffffffff00) == 0) ||
2338 ((Value & 0xffffffffffff00ff) == 0) ||
2339 ((Value & 0xffffffffff00ffff) == 0) ||
2340 ((Value & 0xffffffff00ffffff) == 0) ||
2341 ((Value & 0xffffffffffff00ff) == 0xff) ||
2342 ((Value & 0xffffffffff00ffff) == 0xffff);
2364 if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2429 // i64 value with each byte being either 0 or 0xff.
2430 for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2431 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2514 // Add as immediates when possible. Null MCExpr = 0.
2516 Inst.addOperand(MCOperand::createImm(0));
2545 Inst.addOperand(MCOperand::createReg(0));
2558 assert(TiedOp >= 0 &&
2620 // Shift of #32 is encoded as 0 where permitted
2621 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2712 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2827 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2832 // An ASR value of 32 encodes as 0, so that's how we want to add it to
2836 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
3008 Inst.addOperand(MCOperand::createImm(0));
3011 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3012 // Special case for #-0
3014 Val = 0;
3015 if (Val < 0)
3036 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3037 // Special case for #-0
3038 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
3039 if (Val < 0) Val = -Val;
3041 Inst.addOperand(MCOperand::createReg(0));
3052 Inst.addOperand(MCOperand::createReg(0));
3053 Inst.addOperand(MCOperand::createImm(0));
3061 Inst.addOperand(MCOperand::createImm(0));
3064 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3065 // Special case for #-0
3067 Val = 0;
3068 if (Val < 0)
3078 ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
3087 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
3096 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3097 // Special case for #-0
3098 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
3099 if (Val < 0) Val = -Val;
3101 Inst.addOperand(MCOperand::createReg(0));
3112 Inst.addOperand(MCOperand::createImm(0));
3118 Inst.addOperand(MCOperand::createImm(0));
3122 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3123 // Special case for #-0
3125 Val = 0;
3126 if (Val < 0)
3141 Inst.addOperand(MCOperand::createImm(0));
3148 Inst.addOperand(MCOperand::createImm(0));
3151 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3152 // Special case for #-0
3154 Val = 0;
3155 if (Val < 0)
3170 Inst.addOperand(MCOperand::createImm(0));
3185 Inst.addOperand(MCOperand::createImm(0));
3197 Inst.addOperand(MCOperand::createImm(0));
3222 Inst.addOperand(MCOperand::createImm(0));
3236 Inst.addOperand(MCOperand::createImm(0));
3291 Inst.addOperand(MCOperand::createImm(0));
3303 Inst.addOperand(MCOperand::createImm(0));
3320 Inst.addOperand(MCOperand::createImm(0));
3333 bool isAdd = Imm >= 0;
3334 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3335 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3344 bool isAdd = Imm >= 0;
3345 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3347 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3431 for (I = 0; I < E; I++)
3480 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3497 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3529 unsigned B = Value & 0xff;
3530 B |= 0xe00; // cmode = 0b1110
3540 if (Value >= 256 && Value <= 0xffff)
3541 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3542 else if (Value > 0xffff && Value <= 0xffffff)
3543 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3544 else if (Value > 0xffffff)
3545 Value = (Value >> 24) | 0x600;
3572 unsigned Elem = Value & 0xffff;
3574 Elem = (Elem >> 8) | 0x200;
3596 unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3605 unsigned Imm = 0;
3606 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3609 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3629 Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3799 assert(Regs.size() > 0 && "RegList contains no registers?");
4007 assert((ITMask.Mask & 0xf) == ITMask.Mask);
4066 for (int i=2; i >= 0; --i)
4160 if (Operands[0]->isToken() &&
4161 static_cast<ARMOperand &>(*Operands[0]).getToken() == "cps") {
4295 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
4321 int64_t Imm = 0;
4346 // lsl, ror: 0 <= imm <= 31
4347 // lsr, asr: 0 <= imm <= 32
4349 if (Imm < 0 ||
4357 if (Imm == 0)
4381 return 0;
4443 /// <number> ::= integer in range [0, 15]
4447 if (Name.size() < 2 || Name[0] != CoprocOp)
4454 switch (Name[0]) {
4456 case '0': return 0;
4468 if (Name[0] != '1')
4474 case '0': return 10;
4492 if (CC == ~0U)
4558 if (!CE || CE->getValue() < 0 || CE->getValue() > 255)
4560 "coprocessor option must be an immediate in range [0, 255]");
4634 int EReg = 0;
4811 Index = 0; // Always return a defined index value.
4841 if (Val < 0 || Val > 7)
4922 int Spacing = 0;
5100 .Default(~0U);
5105 Opt = ~0U;
5107 if (Opt == ~0U)
5127 if (Val & ~0xf)
5192 if (Val & ~0xf)
5216 unsigned IFlags = 0;
5218 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
5223 .Default(~0U);
5227 if (Flag == ~0U || (IFlags & Flag))
5252 if (Val > 255 || Val < 0) {
5255 unsigned SYSmvalue = Val & 0xFF;
5270 unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
5278 size_t Start = 0, Next = Mask.find('_');
5285 // 3-0: Mask
5286 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5287 unsigned FlagsVal = 0;
5291 .Case("nzcvq", 0x8) // same as CPSR_f
5292 .Case("g", 0x4) // same as CPSR_s
5293 .Case("nzcvqg", 0xc) // same as CPSR_fs
5294 .Default(~0U);
5296 if (FlagsVal == ~0U) {
5306 for (int i = 0, e = Flags.size(); i != e; ++i) {
5312 .Default(~0U);
5316 if (Flag == ~0U || (FlagsVal & Flag))
5329 // FlagsVal = 0x9;
5331 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5415 .Case("le", 0)
5428 /// lsl #n 'n' in [0,31]
5430 /// n == 32 encoded as n == 0.
5467 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5470 if (Val == 32) Val = 0;
5473 if (Val < 0 || Val > 31)
5474 return Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5485 /// ror #n 'n' in {0, 8, 16, 24}
5513 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5516 if (Val != 8 && Val != 16 && Val != 24 && Val != 0)
5570 (Enc & 0xFF), (Enc & 0xF00) >> 7, Sx1, Ex1, *this));
5594 "expected modified immediate operand: #[0, 255], #even[0-30]");
5596 if (Imm1 & ~0xFF)
5597 return Error(Sx1, "immediate operand must a number in the range [0, 255]");
5619 if (!(Imm2 & ~0x1E)) {
5625 "immediate operand must an even number in the range [0, 30]");
5649 // The LSB must be in the range [0,31]
5650 if (LSB < 0 || LSB > 31)
5651 return Error(E, "'lsb' operand must be in the range [0,31]");
5713 unsigned ShiftImm = 0;
5762 if (isNegative && Val == 0)
5791 Reg, isAdd, ARM_AM::no_shift, 0, S, Tok.getEndLoc(), *this));
5796 // Finds the index of the first CondCode operator, if there is none returns 0
5804 return 0;
5814 return 0;
5847 if (CondOutI != 0) {
5851 *ARMOperand::CreateCCOut(0, Operands[0]->getEndLoc(), *this);
5860 if (CondI != 0) {
5864 llvm::ARMCC::AL, Operands[0]->getEndLoc(), *this);
5874 (CondI == 0 ? ARMCC::AL
5917 if (CondI != 0) {
5921 llvm::ARMCC::AL, Operands[0]->getEndLoc(), *this);
5945 if (CondI != 0) {
5950 *ARMOperand::CreateCondCode(ARMCC::AL, Operands[0]->getEndLoc(), *this);
5981 BaseReg, nullptr, 0, ARM_AM::no_shift, 0, 0, false, S, E, *this));
6017 unsigned Align = 0;
6037 Operands.push_back(ARMOperand::CreateMem(BaseReg, nullptr, 0,
6038 ARM_AM::no_shift, 0, Align, false,
6070 // If the constant was #-0, represent it as
6073 if (isNegative && Val == 0)
6081 Operands.push_back(ARMOperand::CreateMem(BaseReg, AdjustedOffset, 0,
6082 ARM_AM::no_shift, 0, 0, false, S,
6119 unsigned ShiftImm = 0;
6133 ShiftType, ShiftImm, 0, isNegative,
6177 Amount = 0;
6191 // lsl, ror: 0 <= imm <= 31
6192 // lsr, asr: 0 <= imm <= 32
6197 if (Imm < 0 ||
6201 // If <ShiftTy> #0, turn it into a no_shift.
6202 if (Imm == 0)
6204 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
6206 Imm = 0;
6256 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
6288 if (Val > 255 || Val < 0)
6332 if (Res == 0) // success
6401 if (IsNegative && Val == 0)
6578 ProcessorIMod = 0;
6623 if (CC != ~0U) {
6624 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
6643 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
6655 .Default(~0U);
6656 if (IMod != ~0U) {
6657 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
6671 if (VCC != ~0U) {
6672 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
6681 Mnemonic = Mnemonic.slice(0, 2);
6686 Mnemonic = Mnemonic.slice(0, 4);
6689 Mnemonic = Mnemonic.slice(0, 3);
6774 for (unsigned I = 0; I < MnemonicOpsEndInd; ++I) {
7057 for (unsigned I = 0; I < MnemonicOpsEndInd; ++I)
7066 for (unsigned I = 0; I < MnemonicOpsEndInd; ++I)
7075 for (unsigned I = 0; I < MnemonicOpsEndInd; ++I)
7107 size_t Start = 0, Next = Name.find('.');
7130 // encoding, and above that, a 1 bit indicates 'else', and an 0
7366 Mnemonic = Mnemonic.substr(0, 4);
7403 Mnemonic = Name.slice(0, Mnemonic.size() + 1);
7534 return 0;
7581 unsigned RtIndex = Load || !Writeback ? 0 : 1;
7637 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
7666 SMLoc Loc = Operands[0]->getStartLoc();
7679 SMLoc CondLoc = Operands[0]->getEndLoc();
7704 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
7775 unsigned Cond = Inst.getOperand(0).getImm();
7808 const MCRegister RmReg = Inst.getOperand(0).getReg();
7862 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7877 if (Inst.getOperand(0).getReg() == ARM::PC) {
7902 if (Imm > 0 || Imm < -255)
7904 "operand must be in range [0, 255] with a negative sign");
7906 if (Inst.getOperand(0).getReg() == ARM::PC) {
7930 if (Imm > 0 || Imm < -255)
7932 "operand must be in range [0, 255] with a negative sign");
7934 if (Inst.getOperand(0).getReg() == ARM::PC) {
7952 if (Imm > 0 || Imm < -255)
7954 "operand must be in range [0, 255] with a negative sign");
7956 if (Inst.getOperand(0).getReg() == ARM::PC) {
7974 if (Imm > 0 || Imm < -255)
7976 "operand must be in range [0, 255] with a negative sign");
7978 if (Inst.getOperand(0).getReg() == ARM::PC) {
8010 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
8039 unsigned QdIdx = 0, QmIdx = 2;
8086 MCRegister Rn = Inst.getOperand(0).getReg();
8123 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
8141 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
8196 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
8197 0, ListContainsBase);
8217 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8227 if (Inst.getOperand(0).getReg() == ARM::SP &&
8318 unsigned Imm8 = Inst.getOperand(0).getImm();
8322 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
8326 if (Imm8 == 0x14 && Pred != ARMCC::AL)
8338 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) {
8359 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
8368 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
8372 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
8373 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
8399 unsigned Option = Inst.getOperand(0).getImm();
8402 // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
8403 if (Option == 0 && Pred != ARMCC::AL)
8424 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
8493 "Q-register indexes must be 2 and 0 or 3 and 1");
8507 "Q-register indexes must be 2 and 0 or 3 and 1");
8545 MCRegister RdHi = Inst.getOperand(0).getReg();
8641 size_t CopInd = 0;
8949 TmpInst.addOperand(Inst.getOperand(0));
8967 TmpInst.addOperand(Inst.getOperand(0));
8970 TmpInst.addOperand(MCOperand::createReg(0));
8971 TmpInst.addOperand(MCOperand::createImm(0));
8989 TmpInst.addOperand(Inst.getOperand(0));
9006 TmpInst.addOperand(Inst.getOperand(0));
9008 TmpInst.addOperand(MCOperand::createReg(0));
9009 TmpInst.addOperand(MCOperand::createImm(0));
9022 TmpInst.addOperand(Inst.getOperand(0));
9028 llvm::rotr<uint32_t>(Enc & 0xFF, (Enc & 0xF00) >> 7)));
9057 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9073 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9085 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9098 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9111 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9125 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9137 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9150 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9163 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9177 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9189 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9202 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9215 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9228 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9240 if (Inst.getOperand(1).getImm() > 0 &&
9241 Inst.getOperand(1).getImm() <= 0xff &&
9277 Inst.getOperand(0).getReg() != ARM::PC &&
9278 Inst.getOperand(0).getReg() != ARM::SP) {
9294 Value >=0 && Value < 65536) {
9312 Value >=0 && Value < 65536) {
9320 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9325 TmpInst.addOperand(MCOperand::createReg(0)); // S
9334 TmpInst.addOperand(Inst.getOperand(0)); // Rt
9337 TmpInst.addOperand(MCOperand::createImm(0)); // unused offset
9356 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9378 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9379 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9402 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9403 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9405 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9428 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9429 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9431 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9433 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9453 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9454 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9475 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9476 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9477 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9499 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9500 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9501 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9503 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9525 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9526 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9527 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9529 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9531 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9550 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9570 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9571 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9592 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9593 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9595 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9616 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9617 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9619 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9621 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9639 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9644 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9662 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9663 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9669 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9670 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9689 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9690 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9692 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9698 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9699 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9701 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9720 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9721 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9723 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9725 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9731 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9732 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9734 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9736 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9753 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9757 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9758 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9776 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9777 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9782 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9783 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9784 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9803 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9804 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9806 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9811 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9812 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9813 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9815 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9834 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9835 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9837 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9839 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9844 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9845 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9846 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9848 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9850 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9867 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9870 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9888 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9889 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9893 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9894 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9913 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9914 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9916 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9920 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9923 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9942 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9943 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9945 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9947 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9951 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9952 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9954 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9956 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9975 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9976 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9978 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9997 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9998 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10000 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10005 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
10021 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10022 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10024 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10046 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10047 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10049 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10068 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10069 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10071 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10076 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
10092 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10093 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10095 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10117 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10118 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10120 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10122 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10141 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10142 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10144 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10146 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10151 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
10167 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10168 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10170 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10172 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10194 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10195 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10197 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10199 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10218 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10219 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10221 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10223 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10228 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
10244 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10245 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10247 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10249 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10273 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10274 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10276 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10296 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
10297 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10298 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10300 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10321 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10322 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10324 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10344 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10345 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10347 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10349 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10369 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
10370 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10371 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10373 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10375 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10396 TmpInst.addOperand(Inst.getOperand(0)); // Vd
10397 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10399 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10401 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10413 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10428 TmpInst.addOperand(Inst.getOperand(0));
10446 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10449 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10463 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10483 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10493 // MOV rd, rm, LSL #0 is actually a MOV instruction
10494 if (Shift == ARM_AM::lsl && Amount == 0) {
10497 // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
10514 if (Amount == 32) Amount = 0;
10516 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10544 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
10547 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10571 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
10572 // A shift by 32 should be encoded as 0 when permitted
10574 Amt = 0;
10578 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10589 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
10592 TmpInst.addOperand(Inst.getOperand(0)); // Rd
10609 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10624 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10636 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
10641 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10643 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
10654 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
10658 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10673 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
10692 Inst.addOperand(MCOperand::createReg(0)); // cc_out
10696 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10708 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10726 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg())
10728 if (!isARMLowRegister(Inst.getOperand(0).getReg()))
10747 TmpInst.addOperand(Inst.getOperand(0));
10749 TmpInst.addOperand(Inst.getOperand(0));
10782 auto DestReg = Inst.getOperand(0).getReg();
10792 TmpInst.addOperand(Inst.getOperand(0));
10793 TmpInst.addOperand(Inst.getOperand(0));
10803 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
10805 Inst.addOperand(MCOperand::createReg(0)); // cc_out
10842 MCRegister Rn = Inst.getOperand(0).getReg();
10859 MCOperand::createReg(Inst.getOperand(0).getReg()));
10868 MCRegister Rn = Inst.getOperand(0).getReg();
10906 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10915 TmpInst.addOperand(Inst.getOperand(0));
10928 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10937 TmpInst.addOperand(Inst.getOperand(0));
10954 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10956 Inst.getOperand(2).getImm() == 0 &&
10969 TmpInst.addOperand(Inst.getOperand(0));
10980 // rrx shifts and asr/lsr of #32 is encoded as 0
10983 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10987 TmpInst.addOperand(Inst.getOperand(0));
11016 // The exception is for right shifts, where 0 == 32
11017 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
11021 TmpInst.addOperand(Inst.getOperand(0));
11037 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()),
11050 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
11066 TmpInst.addOperand(Inst.getOperand(0));
11086 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
11087 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
11101 TmpInst.addOperand(Inst.getOperand(0));
11103 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
11140 MCOperand &MO = Inst.getOperand(0);
11142 VPTState.CurPosition = 0;
11157 if (Operands[0]->isToken() &&
11158 static_cast<ARMOperand &>(*Operands[0]).getToken() == "nop" &&
11181 for (unsigned OpNo = 0; OpNo < MCID.NumOperands; ++OpNo) {
11198 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
11209 isARMLowRegister(Inst.getOperand(0).getReg()) &&
11220 if (Inst.getOperand(0).getReg() == ARM::SP &&
11225 (Inst.getOperand(0).getReg() == ARM::SP ||
11246 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
11253 if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
11261 if (Inst.getOperand(0).getReg() != Inst.getOperand(3).getReg())
11268 for (unsigned I = 0; I < MCID.NumOperands; ++I)
11278 // slot in the form of an immediate 0, because it can't
11407 unsigned VariantID = 0);
11478 ((ARMOperand &)*Operands[0]).getToken(), FBS);
11480 ((ARMOperand &)*Operands[0]).getLocRange());
11628 getParser().getStreamer().emitCodeAlignment(Align(2), &getSTI(), 0);
11641 getParser().getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0);
11899 int64_t IntegerValue = 0;
11907 } else if (Tag < 32 || Tag % 2 == 0)
12154 int64_t Offset = 0;
12227 ARMOperand &Op = (ARMOperand &)*Operands[0];
12252 Width = 0;
12272 if (Value->getValue() > 0xffff)
12276 if (Value->getValue() > 0xffffffff)
12280 case 0:
12282 if (Value->getValue() < 0xe800)
12284 else if (Value->getValue() >= 0xe8000000)
12372 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
12374 "personality routine index should be in range [0-3]");
12415 if (Opcode & ~0xff)
12468 int64_t Offset = 0;
12527 getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0);
12529 getStreamer().emitValueToAlignment(Align(4), 0, 1, 0);
12575 ARMOperand &Op = (ARMOperand &)*Operands[0];
12579 uint32_t Mask = 0;
12580 for (size_t i = 0; i < RegList.size(); ++i) {
12590 if (!Wide && (Mask & 0x1f00) != 0)
12617 ARMOperand &Op = (ARMOperand &)*Operands[0];
12621 uint32_t Mask = 0;
12622 for (size_t i = 0; i < RegList.size(); ++i) {
12629 if (Mask == 0)
12632 unsigned First = 0;
12633 while ((Mask & 1) == 0) {
12637 if (((Mask + 1) & Mask) != 0)
12641 while ((Mask & 2) != 0) {
12689 if (CC == ~0U)
12708 unsigned Opcode = 0;
12713 if (Byte > 0xff || Byte < 0)
12715 if (Opcode > 0x00ffffff)
12803 unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
12808 if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
12866 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
12897 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[0]);
12938 if (Messages.size() == 0) {
12944 Error(Messages[0].Loc, Messages[0].Message);
13075 if (CE->getValue() == 0)
13158 return ARMOperand::CreateCCOut(0, SMLoc(), *this);