Lines Matching defs:ShiftTy

901     ARM_AM::ShiftOpc ShiftTy;
911     ARM_AM::ShiftOpc ShiftTy;
918     ARM_AM::ShiftOpc ShiftTy;
1481     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
2612       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2623       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
3364                                      PostIdxReg.ShiftTy);
3721     Op->RegShiftedReg.ShiftTy = ShTy;
3735     Op->RegShiftedImm.ShiftTy = ShTy;
3911   CreatePostIdxReg(MCRegister Reg, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3916     Op->PostIdxReg.ShiftTy = ShiftTy;
4058     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
4059       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
4081        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
4086        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
4307   auto ShiftTy = ShiftTyOpt.value();
4323   if (ShiftTy == ARM_AM::rrx) {
4350           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4351           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4358         ShiftTy = ARM_AM::lsl;
4374   if (ShiftReg && ShiftTy != ARM_AM::rrx)
4376         ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc, *this));
4378     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
5712   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5716     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5724       ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E, *this));
6201     // If <ShiftTy> #0, turn it into a no_shift.
10536     ARM_AM::ShiftOpc ShiftTy;
10539     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
10540     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
10541     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
10542     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
10544     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
10561     ARM_AM::ShiftOpc ShiftTy;
10564     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
10565     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
10566     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
10567     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
10573     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
10575     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);