Lines Matching defs:RegNum

865     MCRegister RegNum;
870 MCRegister RegNum;
899 MCRegister RegNum;
1005 return Reg.RegNum;
1374 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg.RegNum);
1378 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg.RegNum);
1478 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
2071 VectorList.RegNum);
2081 .contains(VectorList.RegNum));
2098 .contains(VectorList.RegNum));
2114 VectorList.RegNum);
2133 .contains(VectorList.RegNum));
2501 VectorList.RegNum = DPair;
2508 VectorList.RegNum = DReg;
2536 unsigned RegNum = getCondCode() == ARMCC::AL ? ARM::NoRegister : ARM::CPSR;
2537 Inst.addOperand(MCOperand::createReg(RegNum));
2543 unsigned RegNum = getVPTPred() == ARMVCC::None ? ARM::NoRegister : ARM::P0;
2544 Inst.addOperand(MCOperand::createReg(RegNum));
2551 MCRegister RegNum;
2553 RegNum = ARM::NoRegister;
2560 RegNum = Inst.getOperand(TiedOp).getReg();
2562 Inst.addOperand(MCOperand::createReg(RegNum));
3088 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3353 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3359 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3393 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3395 Inst.addOperand(MCOperand::createReg(Reg.RegNum));
3397 MCRegister DPair = Parser->getDRegFromQReg(Reg.RegNum);
3432 if (RC_in->getRegister(I) == VectorList.RegNum)
3441 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3691 Op->Reg.RegNum = Reg;
3710 Op->Reg.RegNum = Reg;
3838 Op->VectorList.RegNum = Reg;
3850 Op->VectorList.RegNum = Reg;
3863 Op->VectorList.RegNum = Reg;
3914 Op->PostIdxReg.RegNum = Reg;
4057 << RegName(PostIdxReg.RegNum);
4122 << RegName(VectorList.RegNum) << ">";
4126 << RegName(VectorList.RegNum) << ">";
4130 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";