Lines Matching defs:Operands
438 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
441 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
518 bool CarrySetting, OperandVector &Operands,
521 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands,
665 OperandVector &Operands,
669 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands,
671 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, bool Load,
716 SMLoc NameLoc, OperandVector &Operands) override;
724 const OperandVector &Operands) override;
727 OperandVector &Operands, MCStreamer &Out,
730 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
744 SMLoc IDLoc, OperandVector &Operands);
746 OperandVector &Operands);
4156 static unsigned getMnemonicOpsEndInd(const OperandVector &Operands) {
4160 if (Operands[0]->isToken() &&
4161 static_cast<ARMOperand &>(*Operands[0]).getToken() == "cps") {
4162 if (Operands.size() > 1 && Operands[1]->isImm() &&
4163 static_cast<ARMOperand &>(*Operands[1]).getImm()->getKind() ==
4166 static_cast<ARMOperand &>(*Operands[1]).getImm())
4169 static_cast<ARMOperand &>(*Operands[1]).getImm())
4176 while (MnemonicOpsEndInd < Operands.size()) {
4177 auto Op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
4300 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
4315 (ARMOperand *)Operands.pop_back_val().release());
4375 Operands.push_back(ARMOperand::CreateShiftedRegister(
4378 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4390 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4398 Operands.push_back(ARMOperand::CreateReg(Reg, RegStartLoc, RegEndLoc, *this));
4402 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4428 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), SIdx, E,
4485 ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4496 Operands.push_back(
4505 ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4519 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S, *this));
4526 ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4538 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S, *this));
4544 ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4569 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E, *this));
4614 bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
4795 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E, *this));
4799 Operands.push_back(
4852 ParseStatus ARMAsmParser::parseVectorList(OperandVector &Operands) {
4873 Operands.push_back(ARMOperand::CreateReg(Reg, S, E, *this));
4876 Operands.push_back(
4880 Operands.push_back(ARMOperand::CreateVectorListIndexed(
4893 Operands.push_back(ARMOperand::CreateReg(Reg, S, E, *this));
4898 Operands.push_back(
4902 Operands.push_back(ARMOperand::CreateVectorListIndexed(
4908 Operands.push_back(ARMOperand::CreateReg(Reg, S, E, *this));
5062 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E, *this));
5066 Operands.push_back(ARMOperand::CreateVectorListIndexed(
5074 ParseStatus ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
5135 Operands.push_back(
5141 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
5154 Operands.push_back(
5161 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
5200 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
5206 ParseStatus ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
5235 Operands.push_back(
5241 ParseStatus ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
5243 if (static_cast<ARMOperand &>(*Operands.back()).isMSRMask() ||
5244 static_cast<ARMOperand &>(*Operands.back()).isBankedReg())
5257 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S, *this));
5273 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S, *this));
5336 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S, *this));
5342 ParseStatus ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5344 if (static_cast<ARMOperand &>(*Operands.back()).isBankedReg() ||
5345 static_cast<ARMOperand &>(*Operands.back()).isMSRMask())
5360 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S, *this));
5367 ParseStatus ARMAsmParser::parsePKHImm(OperandVector &Operands,
5402 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc, *this));
5407 ParseStatus ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5421 Operands.push_back(ARMOperand::CreateImm(
5431 ParseStatus ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5477 Operands.push_back(
5486 ParseStatus ARMAsmParser::parseRotImm(OperandVector &Operands) {
5519 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc, *this));
5524 ParseStatus ARMAsmParser::parseModImm(OperandVector &Operands) {
5569 Operands.push_back(ARMOperand::CreateModImm(
5581 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1, *this));
5585 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5587 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1, *this));
5621 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2, *this));
5631 ParseStatus ARMAsmParser::parseBitfield(OperandVector &Operands) {
5676 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc, *this));
5681 ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5723 Operands.push_back(
5729 ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5765 Operands.push_back(ARMOperand::CreateImm(
5790 Operands.push_back(ARMOperand::CreatePostIdxReg(
5797 unsigned findCondCodeInd(const OperandVector &Operands,
5800 auto Op = static_cast<ARMOperand &>(*Operands[I]);
5807 unsigned findCCOutInd(const OperandVector &Operands,
5810 auto Op = static_cast<ARMOperand &>(*Operands[I]);
5821 const OperandVector &Operands) {
5822 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
5823 unsigned CondI = findCondCodeInd(Operands, MnemonicOpsEndInd);
5824 unsigned CondOutI = findCCOutInd(Operands, MnemonicOpsEndInd);
5831 if (Operands.size() == MnemonicOpsEndInd + 3) {
5834 if (((ARMOperand &)*Operands[RegRd]).getReg() ==
5835 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 1]).getReg()) {
5845 ((ARMOperand &)*Operands[RegRd]).addRegOperands(Inst, 1);
5848 ((ARMOperand &)*Operands[CondOutI]).addCCOutOperands(Inst, 1);
5851 *ARMOperand::CreateCCOut(0, Operands[0]->getEndLoc(), *this);
5855 ((ARMOperand &)*Operands[RegRn]).addRegOperands(Inst, 1);
5857 ((ARMOperand &)*Operands[RegRm]).addRegOperands(Inst, 1);
5861 ((ARMOperand &)*Operands[CondI]).addCondCodeOperands(Inst, 2);
5864 llvm::ARMCC::AL, Operands[0]->getEndLoc(), *this);
5870 const OperandVector &Operands) {
5871 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
5872 unsigned CondI = findCondCodeInd(Operands, MnemonicOpsEndInd);
5875 : static_cast<ARMOperand &>(*Operands[CondI]).getCondCode());
5903 ARMOperand &op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
5910 ARMOperand &op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
5916 ((ARMOperand &)*Operands[MnemonicOpsEndInd]).addImmOperands(Inst, 1);
5918 ((ARMOperand &)*Operands[CondI]).addCondCodeOperands(Inst, 2);
5921 llvm::ARMCC::AL, Operands[0]->getEndLoc(), *this);
5927 MCInst &Inst, const OperandVector &Operands) {
5929 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
5930 unsigned CondI = findCondCodeInd(Operands, MnemonicOpsEndInd);
5933 assert(Operands.size() == MnemonicOpsEndInd + 6);
5935 ((ARMOperand &)*Operands[MnemonicOpsEndInd]).addRegOperands(Inst, 1); // Rt
5936 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 1])
5938 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 2])
5940 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 3])
5942 // skip second copy of Qd in Operands[6]
5943 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 5])
5946 ((ARMOperand &)*Operands[CondI])
5950 *ARMOperand::CreateCondCode(ARMCC::AL, Operands[0]->getEndLoc(), *this);
5957 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5980 Operands.push_back(ARMOperand::CreateMem(
5986 Operands.push_back(
6037 Operands.push_back(ARMOperand::CreateMem(BaseReg, nullptr, 0,
6044 Operands.push_back(
6081 Operands.push_back(ARMOperand::CreateMem(BaseReg, AdjustedOffset, 0,
6094 Operands.push_back(
6132 Operands.push_back(ARMOperand::CreateMem(BaseReg, nullptr, OffsetReg,
6139 Operands.push_back(
6214 ParseStatus ARMAsmParser::parseFPImm(OperandVector &Operands) {
6215 LLVM_DEBUG(dbgs() << "PARSE FPImm, Ops: " << Operands.size());
6245 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
6247 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[I]);
6256 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
6278 Operands.push_back(
6293 Operands.push_back(
6304 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
6310 ParseStatus ResTy = MatchOperandParserImpl(Operands, Mnemonic);
6329 if (!tryParseRegisterWithWriteBack(Operands))
6331 int Res = tryParseShiftRegister(Operands);
6341 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S, *this));
6361 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E, *this));
6365 return parseMemory(Operands);
6369 return parseRegisterList(Operands, !Mnemonic.starts_with("clr"), false,
6406 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E, *this));
6412 Operands.push_back(ARMOperand::CreateToken(
6438 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E, *this));
6453 Operands.push_back(
6773 bool operandsContainWide(OperandVector &Operands, unsigned MnemonicOpsEndInd) {
6775 auto &Op = static_cast<ARMOperand &>(*Operands[I]);
6788 OperandVector &Operands, unsigned MnemonicOpsEndInd) {
6790 if (operandsContainWide(Operands, MnemonicOpsEndInd))
6792 if (Operands.size() != MnemonicOpsEndInd + 3)
6795 const auto &Op3 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
6796 auto &Op4 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]);
6807 auto &Op5 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 2]);
6867 Operands.erase(Operands.begin() + MnemonicOpsEndInd);
6893 StringRef Mnemonic, OperandVector &Operands, unsigned MnemonicOpsEndInd) {
6894 if (!hasMVE() || Operands.size() <= MnemonicOpsEndInd)
6907 for (auto &Operand : Operands) {
6919 for (auto &Operand : Operands) {
6952 OperandVector &Operands,
6962 if (Operands.size() < IdX + 2)
6965 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[IdX]);
6966 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[IdX + 1]);
6990 Operands.insert(Operands.begin() + IdX + 1,
7001 OperandVector &Operands,
7005 if (Operands.size() < 3 + MnemonicOpsEndInd)
7011 const MCParsedAsmOperand &Op2 = *Operands[MnemonicOpsEndInd + 1];
7046 const MCParsedAsmOperand &Op3 = *Operands[MnemonicOpsEndInd + 2];
7050 Operands.erase(Operands.begin() + MnemonicOpsEndInd + 2);
7051 Operands[MnemonicOpsEndInd + 1] =
7056 void removeCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
7058 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) {
7059 Operands.erase(Operands.begin() + I);
7065 void removeCCOut(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
7067 if (static_cast<ARMOperand &>(*Operands[I]).isCCOut()) {
7068 Operands.erase(Operands.begin() + I);
7074 void removeVPTCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
7076 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) {
7077 Operands.erase(Operands.begin() + I);
7085 SMLoc NameLoc, OperandVector &Operands) {
7125 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc, *this));
7157 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc, *this));
7197 Operands.push_back(ARMOperand::CreateCCOut(
7205 Operands.push_back(ARMOperand::CreateCondCode(
7217 Operands.push_back(ARMOperand::CreateVPTPred(
7223 Operands.push_back(ARMOperand::CreateImm(
7254 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc, *this));
7261 unsigned MnemonicOpsEndInd = Operands.size();
7266 if (parseOperand(Operands, Mnemonic)) {
7272 if (parseOperand(Operands, Mnemonic)) {
7282 Operands, MnemonicOpsEndInd);
7294 CDEConvertDualRegOperand(Mnemonic, Operands, MnemonicOpsEndInd);
7301 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7307 Operands.erase(Operands.begin() + 1);
7308 Operands.erase(Operands.begin());
7312 Operands.insert(Operands.begin(),
7314 Operands.insert(Operands.begin(), ARMOperand::CreateToken(
7317 !shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7323 Operands.erase(Operands.begin() + 1);
7324 Operands.erase(Operands.begin());
7328 Operands.insert(Operands.begin(),
7330 Operands.insert(Operands.begin(),
7333 !shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7338 removeCondCode(Operands, MnemonicOpsEndInd);
7339 Operands.erase(Operands.begin());
7341 Operands.insert(Operands.begin(), ARMOperand::CreateToken(
7347 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7357 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd - 2]);
7359 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd - 1]);
7362 Operands.erase(Operands.begin());
7367 Operands.insert(Operands.begin(),
7374 Operands.insert(Operands.begin() + 1,
7383 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7385 removeVPTCondCode(Operands, MnemonicOpsEndInd);
7392 for (unsigned I = 1; I < Operands.size(); ++I)
7393 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7404 Operands.erase(Operands.begin());
7405 Operands.insert(Operands.begin(),
7416 Operands.size() == MnemonicOpsEndInd + 1 &&
7417 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]).isImm())
7418 removeCondCode(Operands, MnemonicOpsEndInd);
7421 fixupGNULDRDAlias(Mnemonic, Operands, MnemonicOpsEndInd);
7431 if (!isThumb() && Operands.size() > MnemonicOpsEndInd + 1 + (!IsLoad) &&
7435 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7436 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7460 Operands[Idx] = ARMOperand::CreateReg(NewReg, Op1.getStartLoc(),
7462 Operands.erase(Operands.begin() + Idx + 1);
7472 Operands.size() == MnemonicOpsEndInd + 3 &&
7473 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]).isReg() &&
7474 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]).getReg() ==
7476 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]).isReg() &&
7477 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]).getReg() ==
7479 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 2]).isImm()) {
7480 Operands.front() = ARMOperand::CreateToken(Name, NameLoc, *this);
7481 removeCCOut(Operands, MnemonicOpsEndInd);
7526 unsigned getRegListInd(const OperandVector &Operands,
7528 for (unsigned I = MnemonicOpsEndInd; I < Operands.size(); ++I) {
7529 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[I]);
7538 const OperandVector &Operands,
7547 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7551 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7557 const OperandVector &Operands,
7565 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7569 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7573 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7578 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
7588 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7593 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7599 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7602 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7612 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7621 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7625 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7663 const OperandVector &Operands,
7666 SMLoc Loc = Operands[0]->getStartLoc();
7679 SMLoc CondLoc = Operands[0]->getEndLoc();
7680 for (unsigned I = 1; I < Operands.size(); ++I)
7681 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7682 CondLoc = Operands[I]->getStartLoc();
7727 for (unsigned I = 1; I < Operands.size(); ++I)
7728 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7729 PredLoc = Operands[I]->getStartLoc();
7749 if (Operands.size() ==
7752 *Operands[MnemonicOpsEndInd + 1]); // the register list, a dpr_reglist
7786 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ true,
7792 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ true,
7797 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ false,
7803 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ false,
7811 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7816 if (validateLDRDSTRD(Inst, Operands, /*Load*/ false, /*ARMMode*/ true,
7822 if (validateLDRDSTRD(Inst, Operands, /*Load*/ false, /*ARMMode*/ true,
7828 if (validateLDRDSTRD(Inst, Operands, /*Load*/ false, /*ARMMode*/ false,
7853 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
7866 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7872 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7878 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7897 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7903 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7907 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7925 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7931 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7935 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7948 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7953 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7957 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7970 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7975 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7979 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8014 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8058 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8074 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8088 (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8090 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8097 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
8102 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
8107 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8111 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8124 return Error(Operands.back()->getStartLoc(),
8129 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8134 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8142 return Error(Operands.back()->getStartLoc(),
8146 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8149 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8159 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8167 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8177 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8179 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 2, !isMClass()))
8188 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8190 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 2))
8199 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8205 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8209 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 4))
8218 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8229 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8235 if (!(static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]))
8237 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8241 int op = (Operands[MnemonicOpsEndInd]->isImm()) ? MnemonicOpsEndInd
8243 ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]);
8247 return Error(Operands[op]->getStartLoc(), "branch target out of range");
8252 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd])
8254 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8258 int Op = (Operands[MnemonicOpsEndInd]->isImm()) ? MnemonicOpsEndInd
8260 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
8261 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
8266 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8268 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8283 int i = (Operands[MnemonicOpsEndInd]->isImm()) ? MnemonicOpsEndInd
8285 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
8299 int i = (Operands[MnemonicOpsEndInd + 1]->isImm()) ? MnemonicOpsEndInd + 1
8301 MCParsedAsmOperand &Op = *Operands[i];
8309 MCParsedAsmOperand &Op = *Operands[MnemonicOpsEndInd + 1];
8323 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
8327 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
8336 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd])
8339 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8344 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8346 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8349 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8351 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8357 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd])
8360 return Error(Operands[1]->getStartLoc(),
8363 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8365 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8376 Operands[3]->getStartLoc(),
8386 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8404 return Error(Operands[1]->getStartLoc(),
8408 return Error(Operands[1]->getStartLoc(),
8418 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8427 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8434 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]);
8437 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8448 if (Operands[MnemonicOpsEndInd]->getReg() ==
8449 Operands[MnemonicOpsEndInd + 1]->getReg()) {
8450 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8453 if (Operands[MnemonicOpsEndInd]->getReg() ==
8454 Operands[MnemonicOpsEndInd + 2]->getReg()) {
8455 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8465 if (Operands[MnemonicOpsEndInd]->getReg() ==
8466 Operands[MnemonicOpsEndInd + 1]->getReg()) {
8467 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8475 if (Operands[MnemonicOpsEndInd]->getReg() ==
8476 Operands[MnemonicOpsEndInd + 2]->getReg()) {
8477 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8483 if (Operands[MnemonicOpsEndInd + 2]->getReg() !=
8484 Operands[MnemonicOpsEndInd + 4]->getReg())
8485 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8487 if (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 3])
8489 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 5])
8492 return Error(Operands[MnemonicOpsEndInd + 3]->getStartLoc(),
8497 if (Operands[MnemonicOpsEndInd]->getReg() !=
8498 Operands[MnemonicOpsEndInd + 2]->getReg())
8499 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8501 if (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8503 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 3])
8506 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8512 if (Operands[MnemonicOpsEndInd]->getReg() ==
8513 Operands[MnemonicOpsEndInd + 1]->getReg()) {
8514 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8588 return Error(Operands[1]->getStartLoc(),
8591 return Error(Operands[1]->getStartLoc(),
8649 // Operands[2] is the coprocessor operand at syntactic level
8651 return Error(Operands[2]->getStartLoc(),
8917 const OperandVector &Operands,
8923 for (auto &Op : Operands) {
8936 if (Operands.size() ==
8939 *Operands[MnemonicOpsEndInd + 1]); // the register list, a dpr_reglist
9273 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]);
10636 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
10654 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
10673 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
10702 Operands.size() == MnemonicOpsEndInd + 3) {
10713 Operands.size() == MnemonicOpsEndInd + 3) {
10737 int i = (Operands[MnemonicOpsEndInd + 1]->isImm())
10740 MCParsedAsmOperand &Op = *Operands[i];
10844 (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
10846 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
11151 const OperandVector &Operands) {
11157 if (Operands[0]->isToken() &&
11158 static_cast<ARMOperand &>(*Operands[0]).getToken() == "nop" &&
11321 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
11328 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
11334 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
11360 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
11387 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
11411 OperandVector &Operands,
11419 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
11423 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
11433 if (validateInstruction(Inst, Operands, MnemonicOpsEndInd)) {
11446 while (processInstruction(Inst, Operands, MnemonicOpsEndInd, Out))
11473 ReportNearMisses(NearMisses, IDLoc, Operands);
11478 ((ARMOperand &)*Operands[0]).getToken(), FBS);
11480 ((ARMOperand &)*Operands[0]).getLocRange());
12222 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12225 if (parseRegisterList(Operands, true, true) || parseEOL())
12227 ARMOperand &Op = (ARMOperand &)*Operands[0];
12571 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12573 if (parseRegisterList(Operands) || parseEOL())
12575 ARMOperand &Op = (ARMOperand &)*Operands[0];
12613 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12615 if (parseRegisterList(Operands) || parseEOL())
12617 ARMOperand &Op = (ARMOperand &)*Operands[0];
12769 SMLoc IDLoc, OperandVector &Operands) {
12786 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
12794 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
12897 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[0]);
12900 Message.Loc = Operands[MnemonicOpsEndInd]->getStartLoc();
12918 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
12934 SMLoc IDLoc, OperandVector &Operands) {
12936 FilterNearMisses(NearMisses, Messages, IDLoc, Operands);