Lines Matching defs:Op5

6807   auto &Op5 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 2]);
6812                         (Op5.isReg() && Op5.getReg() == ARM::PC);
6815                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6817                        Op5.isImm() && !Op5.isImm0_508s4());
6836   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
6838   const ARMOperand *LastOp = &Op5;
6840   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6866       std::swap(Op4, Op5);