Lines Matching defs:ARM
9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
30 namespace ARM {
137 // (ARM::RegBanks) is unique in the compiler. At some point, it
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
165 ARM::checkPartialMappings();
166 ARM::checkValueMappings();
190 const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
199 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
200 : &ARM::ValueMappings[ARM::GPR3OpsIdx];
221 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
235 ? &ARM::ValueMappings[ARM::GPR3OpsIdx]
236 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
237 &ARM::ValueMappings[ARM::DPR3OpsIdx]});
245 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
246 &ARM::ValueMappings[ARM::GPR3OpsIdx]})
247 : &ARM::ValueMappings[ARM::GPR3OpsIdx];
257 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
258 : &ARM::ValueMappings[ARM::SPR3OpsIdx];
265 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
266 &ARM::ValueMappings[ARM::DPR3OpsIdx],
267 &ARM::ValueMappings[ARM::DPR3OpsIdx],
268 &ARM::ValueMappings[ARM::DPR3OpsIdx]})
269 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
270 &ARM::ValueMappings[ARM::SPR3OpsIdx],
271 &ARM::ValueMappings[ARM::SPR3OpsIdx],
272 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
280 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
281 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
289 getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
290 &ARM::ValueMappings[ARM::DPR3OpsIdx]});
301 ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
302 &ARM::ValueMappings[ARM::DPR3OpsIdx]})
303 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
304 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
315 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
316 &ARM::ValueMappings[ARM::GPR3OpsIdx]})
317 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
318 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
324 {Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
325 : &ARM::ValueMappings[ARM::SPR3OpsIdx],
334 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
344 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
345 &ARM::ValueMappings[ARM::GPR3OpsIdx],
346 &ARM::ValueMappings[ARM::GPR3OpsIdx],
347 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
355 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
356 &ARM::ValueMappings[ARM::GPR3OpsIdx],
357 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
373 auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
374 : &ARM::ValueMappings[ARM::DPR3OpsIdx];
376 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
390 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
391 &ARM::ValueMappings[ARM::GPR3OpsIdx],
392 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
405 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
406 &ARM::ValueMappings[ARM::GPR3OpsIdx],
407 &ARM::ValueMappings[ARM::DPR3OpsIdx]});
415 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
424 OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
425 : &ARM::ValueMappings[ARM::GPR3OpsIdx];
434 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
447 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||