Lines Matching defs:VCTP

18 /// In addition to this, we also look for the presence of the VCTP instruction,
39 /// VPT, VCMP, VPNOT and VCTP won't overwrite VPR.P0 when they update it in a
252 // Return whether the given instruction is predicated upon a VCTP.
257 // We do not know how to convert an else predicate of a VCTP.
263 // Is the VPST, controlling the block entry, predicated upon a VCTP.
333 // We don't know how to convert a block with just a VPT;VCTP into
334 // anything valid once we remove the VCTP. For now just bail out.
413 // Given that MI is a VCTP, check that is equivalent to any other VCTPs
457 dbgs() << "ARM Loops: Found VCTP(s):\n";
601 dbgs() << "ARM Loops: Didn't find a VCTP instruction.\n";
606 assert(!VCTPs.empty() && "VCTP instruction expected but is not set");
629 MachineInstr *VCTP = VCTPs.back();
636 TPNumElements = VCTP->getOperand(1);
642 if (RDA.hasLocalDefBefore(VCTP, NumElements)) {
643 LLVM_DEBUG(dbgs() << "ARM Loops: VCTP operand is defined in the loop.\n");
730 // need to compute an output size that is smaller than the VCTP mask operates
732 // size it extends into, so any VCTP VecSize <= is valid.
733 unsigned VCTPVecSize = getVecSize(*VCTP);
737 LLVM_DEBUG(dbgs() << "ARM Loops: Double width result larger than VCTP "
751 MachineBasicBlock *MBB = VCTP->getParent();
757 &MBB->back(), VCTP->getOperand(1).getReg().asMCReg())) {
760 unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode());
794 !RDA.hasLocalDefBefore(VCTP, VCTP->getOperand(1).getReg())) {
796 &Preheader->back(), VCTP->getOperand(1).getReg().asMCReg())) {
1034 // any VPT predicated instruction is predicated upon VCTP. Any live-out
1105 LLVM_DEBUG(dbgs() << "ARM Loops: Adding VCTP: " << *MI);
1111 // If we find another VCTP, check whether it uses the same value as the main VCTP.
1116 LLVM_DEBUG(dbgs() << "ARM Loops: Found VCTP with a different reaching "
1117 "definition from the main VCTP");
1486 // operand of the VCTP instruction in the vector body, see getCount(), which is