Lines Matching defs:isLd
1522 bool isLd = isLoadSingle(Opcode);
1531 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1534 .addReg(MO.getReg(), (isLd ? getDefRegState(true)
1539 } else if (isLd) {
1787 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1788 bool EvenDeadKill = isLd ?
1791 bool OddDeadKill = isLd ?
1805 unsigned NewOpc = (isLd)
1808 if (isLd) {
1812 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1813 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill))
1829 unsigned NewOpc = (isLd)
1834 unsigned NewOpc2 = (isLd)
1839 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {
1841 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
1843 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1857 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1860 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
1864 if (isLd)
2174 unsigned Base, bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
2216 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
2230 if (I->mayStore() || (!isLd && I->mayLoad()))
2323 bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
2398 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
2405 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
2433 if (isLd) {
2473 if (isLd) {
2566 bool isLd = isLoadSingle(Opc);
2587 if (isLd)