Lines Matching defs:BaseKill

176         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
182         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
628     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
702     int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm
714       BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm
727     bool KillOldBase = BaseKill &&
775     BaseKill = true; // New base is always killed straight away.
794   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)
811        .addReg(Base, getKillRegState(BaseKill));
815     if (!BaseKill)
820     MIB.addReg(Base, getKillRegState(BaseKill));
835     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
905   bool BaseKill = LatestMI->killsRegister(Base, /*TRI=*/nullptr);
911     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,
915     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,
1294   bool BaseKill = BaseOP.isKill();
1326       if (!STI->hasMinSize() || !BaseKill)
1350     .addReg(Base, getKillRegState(BaseKill))
1474   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
1531                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1735                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,
1742       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1751       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1794   bool BaseKill = BaseOp.isKill();
1810         .addReg(BaseReg, getKillRegState(BaseKill))
1818         .addReg(BaseReg, getKillRegState(BaseKill))
1844                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1861                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,