Lines Matching defs:isSEXTLoad

9503   if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
9596     assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) &&
9601     unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
19697                                       bool isSEXTLoad, SDValue &Base,
19703   if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
19756                                      bool isSEXTLoad, SDValue &Base,
19781                                       bool isSEXTLoad, bool IsMasked, bool isLE,
19847   bool isSEXTLoad = false;
19853     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
19862     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
19877                   Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked,
19881       isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
19884       isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
19905   bool isSEXTLoad = false, isNonExt;
19911     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
19922     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
19956               getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked,
19961       isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
19964       isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,