Lines Matching defs:SRL
207 setOperationAction(ISD::SRL, VT, Custom);
270 setOperationAction(ISD::SRL, VT, Custom);
1015 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
1187 setOperationAction(ISD::SRL, MVT::i64, Custom);
1195 // assuming that ISD::SRL and SRA of i64 are already marked custom
1615 setTargetDAGCombine(ISD::SRL);
2016 if (Op.getOpcode() != ISD::SRL)
6380 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
6386 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
6427 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
6465 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
6730 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6759 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6779 if (ShOpc == ISD::SRL) {
6803 // We only lower SRA, SRL of 1 here, all others use generic lowering.
6811 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
6817 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::LSRS1 : ARMISD::ASRS1;
8672 SDValue srl = DAG.getNode(ISD::SRL, dl, MVT::i32, rbit,
8996 Lo = DAG.getNode(ISD::SRL, dl, FromVT, Lo, Amt);
8997 Hi = DAG.getNode(ISD::SRL, dl, FromVT, Hi, Amt);
9150 SDValue Shift = DAG.getNode(ISD::SRL, dl, MVT::i32, Conv,
10154 SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
10189 Val = DAG.getNode(ISD::SRL, dl, MVT::i32,
10248 GRP = DAG.getNode(ISD::SRL, dl, MVT::i32,
10649 case ISD::SRL:
10786 case ISD::SRL:
13851 N->getOpcode() == ISD::SRL) &&
13899 N->getOperand(0).getOpcode() == ISD::SRL) &&
13922 N->getOperand(0).getOpcode() == ISD::SRL) ||
13923 (N->getOpcode() == ISD::SRL &&
14379 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
14412 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14421 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14436 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14447 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14526 SDValue SRL = OR->getOperand(0);
14529 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
14530 SRL = OR->getOperand(1);
14533 if (!isSRL16(SRL) || !isSHL16(SHL))
14538 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
14539 SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)
14542 SDNode *SMULLOHI = SRL.getOperand(0).getNode();
14543 if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) ||
14653 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
14670 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
14915 if (From->getOpcode() == ISD::SRL &&
15009 From1 = DAG.getNode(ISD::SRL, dl, VT, From1,
17809 ISD::SRL, DL, MVT::i32, SHL,
17836 case ISD::SRL:
18213 X = DAG.getNode(ISD::SRL, dl, VT, X,
18516 // CMOV 0, 1, ==, (CMPZ x, y) -> SRL (CTLZ (SUB x, y)), 5
18518 Res = DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::CTLZ, dl, VT, Sub),
18974 case ISD::SRL:
20778 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,