Lines Matching defs:SRA

206     setOperationAction(ISD::SRA, VT, Custom);
269     setOperationAction(ISD::SRA, VT, Custom);
1015     setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
1188   setOperationAction(ISD::SRA,       MVT::i64, Custom);
1195   // assuming that ISD::SRL and SRA of i64 are already marked custom
2024   if (Op.getOpcode() != ISD::SRA)
2039 // Check for a signed 16-bit value. We special case SRA because it makes it
4227     SDValue SRA =
4228         DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4229     SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4247     SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
5053                               DAG.getNode(ISD::SRA, dl, Op.getValueType(),
5505     SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
6380   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
6398   SDValue HiBigShift = Opc == ISD::SRA
6730   assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6735         (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
6746       (N->getOpcode() == ISD::SRA ? ARMISD::VSHLs : ARMISD::VSHLu);
6759   assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6788     } else if (ShOpc == ISD::SRA)
6803   // We only lower SRA, SRL of 1 here, all others use generic lowering.
6811   // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
10650   case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
10787   case ISD::SRA:
12883   // be sign extended somehow or SRA'd into 32-bit values
12894   SDValue SRA = AddeNode->getOperand(0);
12896   if (SRA.getOpcode() != ISD::SRA) {
12897     SRA = AddeNode->getOperand(1);
12899     if (SRA.getOpcode() != ISD::SRA)
12902   if (auto Const = dyn_cast<ConstantSDNode>(SRA.getOperand(1))) {
12908   if (SRA.getOperand(0) != Mul)
13413   if (Shft.getOpcode() != ISD::SRA)
13850   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
14551   // For SMULWT only the SRA is required.
17835   case ISD::SRA:
17839           (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
18973   case ISD::SRA: