Lines Matching defs:DCI
12635 // @param DCI Context.
12640 TargetLowering::DAGCombinerInfo &DCI,
12642 SelectionDAG &DAG = DCI.DAG;
12666 TargetLowering::DAGCombinerInfo &DCI) {
12670 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
12673 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
12691 TargetLowering::DAGCombinerInfo &DCI,
12703 SelectionDAG &DAG = DCI.DAG;
12719 TargetLowering::DAGCombinerInfo &DCI,
12743 SelectionDAG &DAG = DCI.DAG;
12772 TargetLowering::DAGCombinerInfo &DCI,
12776 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
12837 SelectionDAG &DAG = DCI.DAG;
12876 TargetLowering::DAGCombinerInfo &DCI,
12911 SelectionDAG &DAG = DCI.DAG;
12953 TargetLowering::DAGCombinerInfo &DCI,
13009 return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget);
13069 SelectionDAG &DAG = DCI.DAG;
13119 TargetLowering::DAGCombinerInfo &DCI,
13128 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
13145 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
13157 SelectionDAG &DAG = DCI.DAG;
13196 TargetLowering::DAGCombinerInfo &DCI,
13198 SelectionDAG &DAG(DCI.DAG);
13207 return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
13229 TargetLowering::DAGCombinerInfo &DCI,
13232 SelectionDAG &DAG = DCI.DAG;
13251 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
13257 TargetLowering::DAGCombinerInfo &DCI,
13348 LHS = DCI.DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13352 DCI.DAG.getNode(Opcode, dl, MVT::i32, LHS, RHS->getOperand(0));
13356 Reduction = DCI.DAG.getNode(ISD::TRUNCATE, dl, VectorScalarType, Reduction);
13476 TargetLowering::DAGCombinerInfo &DCI,
13481 if (SDValue V = PerformVQDMULHCombine(N, DCI.DAG))
13511 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS);
13516 TargetLowering::DAGCombinerInfo &DCI,
13524 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
13545 SDValue Op1S = DCI.DAG.getSplatValue(Op1);
13568 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13569 DCI.DAG.getConstant(Opc, DL, MVT::i32),
13570 DCI.DAG.getZExtOrTrunc(Op1S, DL, MVT::i32));
13577 TargetLowering::DAGCombinerInfo &DCI,
13581 return PerformAddeSubeCombine(N, DCI, Subtarget);
13584 if (DCI.isBeforeLegalize()) return SDValue();
13586 return AddCombineTo64bitUMAAL(N, DCI, Subtarget);
13594 TargetLowering::DAGCombinerInfo &DCI,
13597 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget))
13601 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget))
13603 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI,
13609 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI))
13971 TargetLowering::DAGCombinerInfo &DCI,
13974 if (DCI.isBeforeLegalize())
14061 SelectionDAG &DAG = DCI.DAG;
14079 TargetLowering::DAGCombinerInfo &DCI,
14085 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
14088 if (SDValue Result = PerformADDVecReduce(N, DCI.DAG, Subtarget))
14092 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget))
14096 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
14122 TargetLowering::DAGCombinerInfo &DCI,
14129 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI))
14132 if (SDValue R = PerformSubCSINCCombine(N, DCI.DAG))
14153 SDValue Negate = DCI.DAG.getNode(ISD::SUB, dl, MVT::i32,
14154 DCI.DAG.getConstant(0, dl, MVT::i32),
14156 return DCI.DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), Negate);
14175 TargetLowering::DAGCombinerInfo &DCI,
14180 SelectionDAG &DAG = DCI.DAG;
14271 TargetLowering::DAGCombinerInfo &DCI,
14273 SelectionDAG &DAG = DCI.DAG;
14282 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14286 return PerformVMULCombine(N, DCI, Subtarget);
14352 DCI.CombineTo(N, Res, false);
14357 TargetLowering::DAGCombinerInfo &DCI,
14360 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14398 SelectionDAG &DAG = DCI.DAG;
14469 TargetLowering::DAGCombinerInfo &DCI,
14475 SelectionDAG &DAG = DCI.DAG;
14503 if (SDValue Result = combineSelectAndUseCommutative(N, true, DCI))
14506 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
14511 if (SDValue Result = CombineANDShift(N, DCI, Subtarget))
14519 TargetLowering::DAGCombinerInfo &DCI,
14556 SelectionDAG &DAG = DCI.DAG;
14579 TargetLowering::DAGCombinerInfo &DCI,
14588 SelectionDAG &DAG = DCI.DAG;
14630 DCI.CombineTo(N, Res, false);
14657 DCI.CombineTo(N, Res, false);
14674 DCI.CombineTo(N, Res, false);
14695 DCI.CombineTo(N, Res, false);
14762 TargetLowering::DAGCombinerInfo &DCI,
14768 SelectionDAG &DAG = DCI.DAG;
14799 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
14801 if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget))
14851 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget))
14855 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
14862 TargetLowering::DAGCombinerInfo &DCI,
14865 SelectionDAG &DAG = DCI.DAG;
14872 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
14875 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
15110 TargetLowering::DAGCombinerInfo &DCI,
15115 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
15126 SelectionDAG &DAG = DCI.DAG;
15142 if (DCI.DAG.getDataLayout().isBigEndian())
15144 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
15175 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N));
15193 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N));
15218 TargetLowering::DAGCombinerInfo &DCI) {
15242 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N),
15243 DCI.DAG.getVTList(ArrayRef(OutTys, HasGlue ? 3 : 2)),
15247 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), NewCopy.getValue(0));
15248 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(1), NewCopy.getValue(1));
15250 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(2),
15262 DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(),
15264 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Load.getValue(0));
15265 DCI.DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1));
15272 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
15273 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI))
15327 TargetLowering::DAGCombinerInfo &DCI,
15333 SelectionDAG &DAG = DCI.DAG;
15350 DCI.AddToWorklist(V.getNode());
15359 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15412 SelectionDAG &DAG = DCI.DAG;
15438 DCI.AddToWorklist(V.getNode());
15445 DCI.AddToWorklist(Vec.getNode());
15450 PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15460 return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
15467 DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
15468 SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT,
15469 DCI.DAG.getConstant(65535, dl, MVT::i32));
15470 return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C);
15476 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
15477 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
15544 TargetLowering::DAGCombinerInfo &DCI) {
15553 SelectionDAG &DAG = DCI.DAG;
15560 DCI.AddToWorklist(Vec.getNode());
15561 DCI.AddToWorklist(V.getNode());
15572 PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15576 if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 ||
15577 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64))
15621 SDValue F64 = DCI.DAG.getNode(
15623 DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0),
15624 DCI.DAG.getConstant(Ext.getConstantOperandVal(1) / 2, dl, MVT::i32));
15626 DCI.DAG.getNode(ARMISD::VMOVRRD, dl, {MVT::i32, MVT::i32}, F64);
15628 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1));
15633 TargetLowering::DAGCombinerInfo &DCI,
15643 return DCI.DAG.getNode(ARMISD::VMOVhr, dl, VT, X);
15645 return DCI.DAG.getNode(ARMISD::VMOVrh, dl, VT, X);
15647 return DCI.DAG.getNode(ISD::BITCAST, dl, VT, X);
15676 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI))
15686 return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Op0.getOperand(Vec),
15687 DCI.DAG.getConstant(SubIdx, dl, MVT::i32));
15708 PerformInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15717 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VecVT) ||
15718 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(SubVT))
15738 Hi = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec,
15739 DCI.DAG.getVectorIdxConstant(NumSubElts, DL));
15741 Lo = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec,
15742 DCI.DAG.getVectorIdxConstant(0, DL));
15745 return DCI.DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Lo, Hi);
15848 TargetLowering::DAGCombinerInfo &DCI) {
15849 SelectionDAG &DAG = DCI.DAG;
16140 DCI.CombineTo(N, NewResults);
16141 DCI.CombineTo(User.N, SDValue(UpdN.getNode(), NumResultVecs));
16215 TargetLowering::DAGCombinerInfo &DCI) {
16234 getPointerConstIncrement(User->getOpcode(), Addr, Inc, DCI.DAG);
16246 getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG);
16256 getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG);
16262 SDValue NewInc = DCI.DAG.getConstant(NewConstInc, SDLoc(N), MVT::i32);
16280 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/true, DCI))
16294 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/false, DCI))
16301 TargetLowering::DAGCombinerInfo &DCI) {
16302 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16305 return CombineBaseUpdate(N, DCI);
16309 TargetLowering::DAGCombinerInfo &DCI) {
16310 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16313 SelectionDAG &DAG = DCI.DAG;
16416 DCI.CombineTo(N, NewResults);
16417 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
16429 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
16430 SelectionDAG &DAG = DCI.DAG;
16488 DCI.CombineTo(Use.getUser(), SDValue(VLDDup.getNode(), ResNo));
16497 DCI.CombineTo(VLD, VLDDupResults);
16505 TargetLowering::DAGCombinerInfo &DCI,
16514 if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT))
16516 SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT,
16518 return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract);
16523 if (CombineVLDDUP(N, DCI))
16543 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
16586 TargetLowering::DAGCombinerInfo &DCI,
16592 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
16593 return CombineBaseUpdate(N, DCI);
16856 TargetLowering::DAGCombinerInfo &DCI,
16865 if (SDValue Store = PerformTruncatingStoreCombine(St, DCI.DAG))
16869 if (SDValue NewToken = PerformSplittingToNarrowingStores(St, DCI.DAG))
16873 if (SDValue NewChain = PerformExtractFpToIntStores(St, DCI.DAG))
16876 PerformSplittingMVETruncToNarrowingStores(St, DCI.DAG))
16887 SelectionDAG &DAG = DCI.DAG;
16910 SelectionDAG &DAG = DCI.DAG;
16921 DCI.AddToWorklist(Vec.getNode());
16922 DCI.AddToWorklist(ExtElt.getNode());
16923 DCI.AddToWorklist(V.getNode());
16931 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
16932 return CombineBaseUpdate(N, DCI);
17438 TargetLowering::DAGCombinerInfo &DCI) {
17456 return DCI.DAG.getNode(Op1->getOpcode(), SDLoc(Op1), N->getValueType(0),
17468 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
17469 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
17471 if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, DCI))
17478 TargetLowering::DAGCombinerInfo &DCI) {
17487 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
17488 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
17494 TargetLowering::DAGCombinerInfo &DCI) {
17506 SDValue NewBinOp = DCI.DAG.getNode(N->getOpcode(), DL, VT,
17509 return DCI.DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask());
17544 DAGCombinerInfo &DCI) const {
17545 SelectionDAG &DAG = DCI.DAG;
17716 if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI))
17733 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
17776 TargetLowering::DAGCombinerInfo &DCI,
17778 SelectionDAG &DAG = DCI.DAG;
17784 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
18275 TargetLowering::DAGCombinerInfo &DCI,
18340 SelectionDAG &DAG = DCI.DAG;
18615 TargetLowering::DAGCombinerInfo &DCI,
18617 SelectionDAG &DAG = DCI.DAG;
18646 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI))
18655 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const {
18656 SelectionDAG &DAG = DCI.DAG;
18725 if (!DCI.isAfterLegalizeDAG())
18824 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const {
18825 SelectionDAG &DAG = DCI.DAG;
18891 if (!DCI.isAfterLegalizeDAG())
18928 DAGCombinerInfo &DCI) const {
18932 case ISD::SELECT: return PerformSELECTCombine(N, DCI, Subtarget);
18933 case ISD::VSELECT: return PerformVSELECTCombine(N, DCI, Subtarget);
18934 case ISD::SETCC: return PerformVSetCCToVCTPCombine(N, DCI, Subtarget);
18935 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget);
18936 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget);
18937 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
18938 case ISD::SUB: return PerformSUBCombine(N, DCI, Subtarget);
18939 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
18940 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
18941 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
18942 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
18944 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget);
18946 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget);
18947 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget);
18948 case ARMISD::BFI: return PerformBFICombine(N, DCI.DAG);
18949 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
18950 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
18951 case ARMISD::VMOVhr: return PerformVMOVhrCombine(N, DCI);
18952 case ARMISD::VMOVrh: return PerformVMOVrhCombine(N, DCI.DAG);
18953 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget);
18954 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
18955 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
18957 return PerformExtractEltCombine(N, DCI, Subtarget);
18958 case ISD::SIGN_EXTEND_INREG: return PerformSignExtendInregCombine(N, DCI.DAG);
18959 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI);
18960 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
18961 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget);
18962 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI.DAG, Subtarget);
18965 return PerformVCVTCombine(N, DCI.DAG, Subtarget);
18967 return PerformFADDCombine(N, DCI.DAG, Subtarget);
18969 return PerformVMulVCTPCombine(N, DCI.DAG, Subtarget);
18971 return PerformIntrinsicCombine(N, DCI);
18975 return PerformShiftCombine(N, DCI, Subtarget);
18979 return PerformExtendCombine(N, DCI.DAG, Subtarget);
18981 return PerformFPExtendCombine(N, DCI.DAG, Subtarget);
18986 return PerformMinMaxCombine(N, DCI.DAG, Subtarget);
18988 return PerformCMOVCombine(N, DCI.DAG);
18990 return PerformBRCONDCombine(N, DCI.DAG);
18992 return PerformCMPZCombine(N, DCI.DAG);
18996 return PerformCSETCombine(N, DCI.DAG);
18998 return PerformLOADCombine(N, DCI, Subtarget);
19003 return PerformVLDCombine(N, DCI);
19005 return PerformARMBUILD_VECTORCombine(N, DCI);
19007 return PerformBITCASTCombine(N, DCI, Subtarget);
19009 return PerformPREDICATE_CASTCombine(N, DCI);
19011 return PerformVECTOR_REG_CASTCombine(N, DCI.DAG, Subtarget);
19013 return PerformMVETruncCombine(N, DCI);
19016 return PerformMVEExtCombine(N, DCI);
19018 return PerformVCMPCombine(N, DCI.DAG, Subtarget);
19020 return PerformVECREDUCE_ADDCombine(N, DCI.DAG, Subtarget);
19033 return PerformReduceShuffleCombine(N, DCI.DAG);
19035 return PerformVMOVNCombine(N, DCI);
19038 return PerformVQMOVNCombine(N, DCI);
19040 return PerformVQDMULHCombine(N, DCI);
19044 return PerformLongShiftCombine(N, DCI.DAG);
19048 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
19055 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
19066 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
19067 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
19076 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) ||
19077 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI)))
19086 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) ||
19087 (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI)))
19094 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
19095 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
19105 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
19106 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
19140 return PerformVLDCombine(N, DCI);
19145 return PerformMVEVLDCombine(N, DCI);