Lines Matching defs:CondCode
522 const ISD::CondCode Cond;
593 const ISD::CondCode Cond;
690 const ISD::CondCode Cond;
2050 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
2067 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2073 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2075 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2077 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2078 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2079 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2080 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2081 case ISD::SETO: CondCode = ARMCC::VC; break;
2082 case ISD::SETUO: CondCode = ARMCC::VS; break;
2083 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2084 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2085 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2087 case ISD::SETULT: CondCode = ARMCC::LT; break;
2089 case ISD::SETULE: CondCode = ARMCC::LE; break;
2091 case ISD::SETUNE: CondCode = ARMCC::NE; break;
4253 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4255 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4839 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4942 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4948 switch (CondCode) {
4951 CondCode = ARMCC::PL;
4954 CondCode = ARMCC::MI;
4960 switch (CondCode) {
4970 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5262 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5268 CondCode = ARMCC::GE;
5273 CondCode = ARMCC::GT;
5293 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5299 CondCode = ARMCC::VS;
5307 CondCode = ARMCC::EQ;
5336 static bool isGTorGE(ISD::CondCode CC) {
5340 static bool isLTorLE(ISD::CondCode CC) {
5352 const ISD::CondCode CC, const SDValue K) {
5382 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5392 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5447 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5517 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5597 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5598 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5599 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5613 ARMCC::CondCodes CondCode, CondCode2;
5614 FPCCToARMCC(CC, CondCode, CondCode2);
5627 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5629 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5630 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5638 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5717 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5754 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5755 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5787 ARMCC::CondCodes CondCode =
5789 CondCode = ARMCC::getOppositeCondition(CondCode);
5790 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5801 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5839 ARMCC::CondCodes CondCode =
5841 CondCode = ARMCC::getOppositeCondition(CondCode);
5842 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5862 ARMCC::CondCodes CondCode, CondCode2;
5863 FPCCToARMCC(CC, CondCode, CondCode2);
5865 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
6837 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10561 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
10578 ARMCC::CondCodes CondCode, CondCode2;
10579 FPCCToARMCC(CC, CondCode, CondCode2);
10583 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
13266 ISD::CondCode CC;
13520 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18237 static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm,
18289 ISD::CondCode CC;
18320 auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
18327 auto IsFalseIfZero = [](ISD::CondCode CC, int Imm) {