Lines Matching defs:ARMTargetLowering
171 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
229 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
234 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
239 void ARMTargetLowering::setAllExpand(MVT VT) {
252 void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
259 void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
497 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
872 // ARMTargetLowering::addTypeForNEON method for details.
880 // ARMTargetLowering::addTypeForNEON method for details.
1654 bool ARMTargetLowering::useSoftFloat() const {
1669 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1706 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1920 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1938 ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1962 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1976 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1981 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
2103 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2145 CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2150 CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2157 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2182 SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2196 SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2213 SDValue ARMTargetLowering::LowerCallResult(
2310 std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2343 ARMTargetLowering::ByValCopyKind ARMTargetLowering::ByValNeedsCopyForTailCall(
2390 void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2429 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3051 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3106 bool ARMTargetLowering::IsEligibleForTailCallOptimization(
3241 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3284 ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3460 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3532 bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3564 SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3606 unsigned ARMTargetLowering::getJumpTableEncoding() const {
3615 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3670 ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3714 ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3771 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3812 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3864 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3908 static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
4004 bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
4013 SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
4026 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
4093 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
4118 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
4151 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
4160 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
4166 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
4173 SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
4214 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4434 SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4479 int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4533 void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4552 bool ARMTargetLowering::splitValueIntoRegisterParts(
4568 SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4584 SDValue ARMTargetLowering::LowerFormalArguments(
4839 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4975 SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4994 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
5064 ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
5109 SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
5200 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5312 SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5476 bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5486 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5715 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5763 SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5799 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5877 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5943 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
6063 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
6083 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6165 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
6189 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
6209 Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
6295 SDValue ARMTargetLowering::ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
6370 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
6413 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
6449 SDValue ARMTargetLowering::LowerGET_ROUNDING(SDValue Op,
6472 SDValue ARMTargetLowering::LowerSET_ROUNDING(SDValue Op,
6514 SDValue ARMTargetLowering::LowerSET_FPMODE(SDValue Op,
6542 SDValue ARMTargetLowering::LowerRESET_FPMODE(SDValue Op,
7172 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
7949 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
8219 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
8456 bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
9095 SDValue ARMTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
9961 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
10036 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
10055 ARMTargetLowering::ArgListTy Args;
10078 ARMTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10116 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
10139 void ARMTargetLowering::ExpandDIV_Windows(
10199 void ARMTargetLowering::LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
10555 SDValue ARMTargetLowering::LowerFSETCC(SDValue Op, SelectionDAG &DAG) const {
10593 SDValue ARMTargetLowering::LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const {
10602 SDValue ARMTargetLowering::LowerFP_TO_BF16(SDValue Op,
10613 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10773 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
10846 void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
10974 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
11508 ARMTargetLowering::EmitStructByval(MachineInstr &MI,
11752 ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
11827 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
12033 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
12447 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
13848 ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
13895 bool ARMTargetLowering::isDesirableToCommuteXorWithShift(
13919 bool ARMTargetLowering::shouldFoldConstantShiftPairToMask(
13936 bool ARMTargetLowering::shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
13941 bool ARMTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
13950 bool ARMTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
17543 SDValue ARMTargetLowering::PerformIntrinsicCombine(SDNode *N,
18142 SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {
18402 ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const {
18434 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
18654 SDValue ARMTargetLowering::PerformMVETruncCombine(
18823 SDValue ARMTargetLowering::PerformMVEExtCombine(
18927 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
19153 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
19158 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,
19231 EVT ARMTargetLowering::getOptimalMemOpType(
19259 bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
19267 bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
19276 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19297 bool ARMTargetLowering::isFNegFree(EVT VT) const {
19315 Type *ARMTargetLowering::shouldConvertSplatType(ShuffleVectorInst *SVI) const {
19328 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
19358 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19384 bool ARMTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
19523 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
19561 bool ARMTargetLowering::isLegalT1ScaledAddressingMode(const AddrMode &AM,
19578 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
19644 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19660 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
19674 bool ARMTargetLowering::isMulAddWithConstProfitable(SDValue AddNode,
19837 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
19897 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
19986 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20105 bool ARMTargetLowering::targetShrinkDemandedConstant(
20187 bool ARMTargetLowering::SimplifyDemandedBitsForTargetNode(
20229 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
20260 const char *ARMTargetLowering::LowerXConstraint(EVT ConstraintVT) const {
20282 ARMTargetLowering::ConstraintType
20283 ARMTargetLowering::getConstraintType(StringRef Constraint) const {
20313 ARMTargetLowering::getSingleConstraintMatchWeight(
20345 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
20421 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
20628 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
20701 SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {
20754 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
20795 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
20854 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
20888 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
20905 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
20924 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
21155 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
21165 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
21173 Instruction *ARMTargetLowering::makeDMB(IRBuilderBase &Builder,
21199 Instruction *ARMTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
21224 Instruction *ARMTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
21247 ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
21269 ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
21286 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
21314 ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
21334 bool ARMTargetLowering::shouldInsertFencesForAtomic(
21339 bool ARMTargetLowering::useLoadStackGuardNode(const Module &M) const {
21344 void ARMTargetLowering::insertSSPDeclarations(Module &M) const {
21360 Value *ARMTargetLowering::getSDagStackGuard(const Module &M) const {
21367 Function *ARMTargetLowering::getSSPStackGuardCheck(const Module &M) const {
21374 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
21403 bool ARMTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
21407 bool ARMTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
21411 bool ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(
21427 ARMTargetLowering::preferredShiftLegalizationStrategy(
21435 Value *ARMTargetLowering::emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy,
21470 void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
21477 Value *ARMTargetLowering::emitStoreConditional(IRBuilderBase &Builder,
21512 bool ARMTargetLowering::alignLoopsWithOptSize() const {
21519 ARMTargetLowering::getNumInterleavedAccesses(VectorType *VecTy,
21524 bool ARMTargetLowering::isLegalInterleavedAccessType(
21560 unsigned ARMTargetLowering::getMaxSupportedInterleaveFactor() const {
21579 bool ARMTargetLowering::lowerInterleavedLoad(
21722 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
21911 Align ARMTargetLowering::getABIAlignmentForCallingConv(
21927 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
21943 Register ARMTargetLowering::getExceptionPointerRegister(
21950 Register ARMTargetLowering::getExceptionSelectorRegister(
21957 void ARMTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
21963 void ARMTargetLowering::insertCopiesSplitCSR(
22004 void ARMTargetLowering::finalizeLowering(MachineFunction &MF) const {
22009 bool ARMTargetLowering::isComplexDeinterleavingSupported() const {
22013 bool ARMTargetLowering::isComplexDeinterleavingOperationSupported(
22038 Value *ARMTargetLowering::createComplexDeinterleavingIR(