Lines Matching defs:V0

328   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
329   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
330   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
331   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
334   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
335   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
336   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1844 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1845   SDLoc dl(V0.getNode());
1850   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1855 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1856   SDLoc dl(V0.getNode());
1861   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1866 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1867   SDLoc dl(V0.getNode());
1872   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1877 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1878   SDLoc dl(V0.getNode());
1883   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1888 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1890   SDLoc dl(V0.getNode());
1897   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1903 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1905   SDLoc dl(V0.getNode());
1912   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1918 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1920   SDLoc dl(V0.getNode());
1927   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
2309       SDValue V0 = N->getOperand(Vec0Idx + 0);
2312         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2320         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2365   SDValue V0 = N->getOperand(Vec0Idx + 0);
2371   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2484   SDValue V0 = N->getOperand(Vec0Idx + 0);
2488       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2490       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2497       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2499       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
5764     SDValue V0 = N->getOperand(i+1);
5766     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();