Lines Matching defs:Ops
227 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
230 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
234 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc);
236 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, EVT InactiveTy);
1642 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
1645 MVT::Other, Ops);
1652 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
1655 MVT::Other, Ops);
1683 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)),
1686 MVT::i32, MVT::Other, Ops);
1731 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
1734 MVT::Other, Ops);
1827 SDValue Ops[] = {Base,
1834 N->getValueType(0), MVT::Other, Ops);
1850 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1851 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1861 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1862 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1872 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1873 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1883 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1884 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1897 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1899 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1912 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1914 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1927 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1929 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
2166 SmallVector<SDValue, 7> Ops;
2172 Ops.push_back(MemAddr);
2173 Ops.push_back(Align);
2182 Ops.push_back(Inc);
2186 Ops.push_back(Reg0);
2188 Ops.push_back(Pred);
2189 Ops.push_back(Reg0);
2190 Ops.push_back(Chain);
2191 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2208 Ops.push_back(SDValue(VLdA, 1));
2209 Ops.push_back(Align);
2215 Ops.push_back(Reg0);
2217 Ops.push_back(SDValue(VLdA, 0));
2218 Ops.push_back(Pred);
2219 Ops.push_back(Reg0);
2220 Ops.push_back(Chain);
2221 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
2300 SmallVector<SDValue, 7> Ops;
2331 Ops.push_back(MemAddr);
2332 Ops.push_back(Align);
2341 Ops.push_back(Inc);
2346 Ops.push_back(Reg0);
2348 Ops.push_back(SrcReg);
2349 Ops.push_back(Pred);
2350 Ops.push_back(Reg0);
2351 Ops.push_back(Chain);
2352 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2383 Ops.push_back(SDValue(VStA, 0));
2384 Ops.push_back(Align);
2390 Ops.push_back(Reg0);
2392 Ops.push_back(RegSeq);
2393 Ops.push_back(Pred);
2394 Ops.push_back(Reg0);
2395 Ops.push_back(Chain);
2397 Ops);
2473 SmallVector<SDValue, 8> Ops;
2474 Ops.push_back(MemAddr);
2475 Ops.push_back(Align);
2480 Ops.push_back(IsImmUpdate ? Reg0 : Inc);
2501 Ops.push_back(SuperReg);
2502 Ops.push_back(getI32Imm(Lane, dl));
2503 Ops.push_back(Pred);
2504 Ops.push_back(Reg0);
2505 Ops.push_back(Chain);
2509 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2532 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
2534 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
2535 Ops.push_back(PredicateMask);
2536 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2540 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
2543 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
2544 Ops.push_back(PredicateMask);
2545 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2546 Ops.push_back(Inactive);
2550 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) {
2551 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32));
2552 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2553 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2557 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
2559 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32));
2560 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2561 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2562 Ops.push_back(SDValue(
2569 SmallVector<SDValue, 8> Ops;
2583 Ops.push_back(N->getOperand(2)); // vector of base addresses
2586 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate offset
2589 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4));
2591 AddEmptyMVEPredicateToOps(Ops, Loc);
2593 Ops.push_back(N->getOperand(0)); // chain
2600 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), VTs, Ops);
2612 SmallVector<SDValue, 8> Ops;
2615 Ops.push_back(N->getOperand(1));
2616 Ops.push_back(N->getOperand(2));
2621 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count
2623 Ops.push_back(N->getOperand(3));
2630 Ops.push_back(getI32Imm(SatBit, Loc));
2635 Ops.push_back(getAL(CurDAG, Loc));
2636 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2638 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2645 SmallVector<SDValue, 8> Ops;
2651 Ops.push_back(N->getOperand(FirstInputOp));
2652 Ops.push_back(N->getOperand(FirstInputOp + 1));
2661 Ops.push_back(CarryIn);
2666 AddMVEPredicateToOps(Ops, Loc,
2670 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0));
2672 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2677 SmallVector<SDValue, 8> Ops;
2681 Ops.push_back(N->getOperand(1));
2682 Ops.push_back(N->getOperand(2));
2684 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count
2687 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4));
2689 AddEmptyMVEPredicateToOps(Ops, Loc);
2691 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), ArrayRef(Ops));
2735 SmallVector<SDValue, 8> Ops;
2738 Ops.push_back(N->getOperand(4));
2739 Ops.push_back(N->getOperand(5));
2742 Ops.push_back(N->getOperand(6));
2743 Ops.push_back(N->getOperand(7));
2746 AddMVEPredicateToOps(Ops, Loc, N->getOperand(8));
2748 AddEmptyMVEPredicateToOps(Ops, Loc);
2750 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2812 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
2814 CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops);
2822 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
2824 CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);
2858 SmallVector<SDValue, 8> Ops;
2865 Ops.push_back(N->getOperand(OpIdx++)); // base
2867 Ops.push_back(N->getOperand(OpIdx++)); // limit
2871 Ops.push_back(getI32Imm(ImmValue, Loc));
2874 AddMVEPredicateToOps(Ops, Loc, N->getOperand(OpIdx), Inactive);
2876 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0));
2878 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2885 SmallVector<SDValue, 8> Ops;
2892 Ops.push_back(getI32Imm(ImmCoprocVal, Loc));
2901 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0));
2906 Ops.push_back(N->getOperand(OpIdx++));
2911 Ops.push_back(getI32Imm(ImmVal, Loc));
2917 Ops.push_back(Pred);
2918 Ops.push_back(PredReg);
2922 SDNode *InstrNode = CurDAG->getMachineNode(Opcode, Loc, MVT::Untyped, Ops);
3011 SmallVector<SDValue, 6> Ops;
3012 Ops.push_back(MemAddr);
3013 Ops.push_back(Align);
3023 Ops.push_back(Reg0);
3027 Ops.push_back(Inc);
3038 Ops.push_back(SDValue(VLdA, 0));
3042 Ops.push_back(Pred);
3043 Ops.push_back(Reg0);
3044 Ops.push_back(Chain);
3046 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
3236 SmallVector<SDValue, 3> Ops{
3238 AddEmptyMVEPredicateToOps(Ops, SDLoc(N), Type);
3259 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), Type, Ops));
3296 SmallVector<SDValue, 3> Ops{Node->getOperand(0),
3298 AddEmptyMVEPredicateToOps(Ops, dl, Type);
3300 ReplaceNode(N, CurDAG->getMachineNode(Opcode, dl, Type, Ops));
3364 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3367 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3376 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
3378 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
3383 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3387 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3408 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3412 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3430 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3434 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3451 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3455 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3514 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
3518 CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops);
3570 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),
3573 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
3575 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
3578 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
3659 SDValue Ops[] = {ST->getValue(),
3666 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops);
3705 SDValue Ops[] = {
3712 Ops);
3714 SDValue Ops[] = {
3722 Ops);
3758 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
3761 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3805 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3806 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
3809 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3811 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
3824 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3825 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
3828 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3830 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
3866 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
3869 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
3872 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
3876 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops));
3911 SDValue Ops[] = { N0.getOperand(0), Imm16,
3913 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
3922 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
3926 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops));
3931 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3935 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
3938 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3944 MVT::i32, MVT::i32, Ops));
3950 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3954 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
3957 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3963 MVT::i32, MVT::i32, Ops));
3991 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
3994 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
4032 SDValue Ops[] = { N->getOperand(1),
4036 SDNode *New = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
4056 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain};
4058 {MVT::Untyped, MVT::Other}, Ops);
4087 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain};
4088 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops);
4095 SDValue Ops[] = { N->getOperand(1),
4100 CurDAG->getVTList(MVT::i32, MVT::Other), Ops);
4178 SDValue Ops[] = {N1, Tmp2, CurDAG->getRegister(ARM::CPSR, MVT::i32), Chain,
4180 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Ops);
4201 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32),
4204 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops);
4207 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
4210 Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
4243 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
4245 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
4259 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg};
4260 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
4271 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg};
4272 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
4282 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg};
4283 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
4715 SmallVector<SDValue, 5> Ops;
4716 Ops.push_back(getI32Imm(N->getConstantOperandVal(2), dl)); /* coproc */
4717 Ops.push_back(getI32Imm(N->getConstantOperandVal(3), dl)); /* opc */
4718 Ops.push_back(getI32Imm(N->getConstantOperandVal(4), dl)); /* CRm */
4724 Ops.push_back(getAL(CurDAG, dl));
4725 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4728 Ops.push_back(Chain);
4733 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
4757 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl),
4759 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
4810 SmallVector<SDValue, 7> Ops;
4812 Ops.push_back(Val0);
4813 Ops.push_back(Val1);
4816 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
4817 Ops.push_back(MemAddr);
4818 Ops.push_back(getAL(CurDAG, dl));
4819 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4820 Ops.push_back(Chain);
4826 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
5177 SDValue Ops[] = { Src, Src, Pred, Reg0 };
5178 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops);
5188 SDValue Ops[] = { Src, Pred, Reg0 };
5189 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops);
5357 std::vector<SDValue> &Ops) {
5368 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32));
5480 std::vector<SDValue> Ops;
5481 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
5483 if (!Ops.empty()) {
5490 if (Ops.size() == 5){
5494 assert(Ops.size() == 3 &&
5500 Ops.push_back(getAL(CurDAG, DL));
5501 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
5502 Ops.push_back(N->getOperand(0));
5503 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops));
5511 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32),
5516 DL, MVT::i32, MVT::Other, Ops));
5541 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
5544 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops));
5556 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
5560 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops));
5567 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
5570 DL, MVT::i32, MVT::Other, Ops));
5575 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
5579 MVT::i32, MVT::Other, Ops));
5595 std::vector<SDValue> Ops;
5596 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
5598 if (!Ops.empty()) {
5604 if (Ops.size() == 5) {
5606 Ops.insert(Ops.begin()+2, N->getOperand(2));
5608 assert(Ops.size() == 3 &&
5612 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2);
5615 Ops.push_back(getAL(CurDAG, DL));
5616 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
5617 Ops.push_back(N->getOperand(0));
5619 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
5626 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2),
5631 DL, MVT::Other, Ops));
5649 Ops = { N->getOperand(2), getAL(CurDAG, DL),
5651 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
5667 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
5670 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops));
5679 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2),
5683 DL, MVT::Other, Ops));
5793 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
5794 Ops.push_back(T1.getValue(1));
5795 CurDAG->UpdateNodeOperands(GU, Ops);