Lines Matching defs:NumAlignedDPRCS2Regs

173                         unsigned NumAlignedDPRCS2Regs);
187                        unsigned NumAlignedDPRCS2Regs,
282     if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1838 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1843                                     unsigned NumAlignedDPRCS2Regs,
1857     if (DNum > NumAlignedDPRCS2Regs - 1)
1890       .addImm(8 * NumAlignedDPRCS2Regs)
1913   // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1919   if (NumAlignedDPRCS2Regs >= 6) {
1930     NumAlignedDPRCS2Regs -= 4;
1938   if (NumAlignedDPRCS2Regs >= 4) {
1949     NumAlignedDPRCS2Regs -= 4;
1953   if (NumAlignedDPRCS2Regs >= 2) {
1963     NumAlignedDPRCS2Regs -= 2;
1967   if (NumAlignedDPRCS2Regs) {
1985                         unsigned NumAlignedDPRCS2Regs) {
1993   switch(NumAlignedDPRCS2Regs) {
2011 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
2016                                       unsigned NumAlignedDPRCS2Regs,
2047   // Now restore NumAlignedDPRCS2Regs registers starting from d8.
2051   if (NumAlignedDPRCS2Regs >= 6) {
2061     NumAlignedDPRCS2Regs -= 4;
2069   if (NumAlignedDPRCS2Regs >= 4) {
2078     NumAlignedDPRCS2Regs -= 4;
2082   if (NumAlignedDPRCS2Regs >= 2) {
2090     NumAlignedDPRCS2Regs -= 2;
2094   if (NumAlignedDPRCS2Regs)
2120   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
2137   auto CheckRegArea = [PushPopSplit, NumAlignedDPRCS2Regs,
2139     return getSpillArea(Reg, PushPopSplit, NumAlignedDPRCS2Regs, RegInfo) ==
2163   if (NumAlignedDPRCS2Regs)
2164     emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
2180   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
2186   if (NumAlignedDPRCS2Regs)
2187     emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
2194   auto CheckRegArea = [PushPopSplit, NumAlignedDPRCS2Regs,
2196     return getSpillArea(Reg, PushPopSplit, NumAlignedDPRCS2Regs, RegInfo) ==