Lines Matching defs:isZExt

187                     bool isZExt);
189                      MaybeAlign Alignment = std::nullopt, bool isZExt = true,
198     unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
897                               MaybeAlign Alignment, bool isZExt,
910           Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
912           Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
914         if (isZExt) {
930           Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
932           Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
934         Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1336                              bool isZExt) {
1359       Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1421     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1424       SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1545                                        /*isZExt*/!isSigned);
1952         Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1961         Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2136       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2137         SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2605                                     bool isZExt) {
2690   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2692   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2750   bool isZExt = isa<ZExtInst>(I);
2762   unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2900   uint8_t isZExt     : 1;
2930   bool isZExt;
2936       isZExt = FLE.isZExt;
2946   if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlign(), isZExt, false))